计算机组织与结构课件全分单元Ch161章节幻灯片.pptVIP

* * * * * * * * * ISZ – Execute –T4 0 +1 ISZ – Execute –T5 write Conditional code 0 Execute Cycle (ISZ) ISZ X – if ((X)+1)=0, Skip(小跳 ) t1: Ad(MBR)-MAR t2: (MAR)-Memory read-Memory t3: Memory-MBR t4: (MBR) + 1 - MBR t5: if (MBR) == 0 then (PC) +1 - PC (MBR) -Memory 回存 (MAR) -Memory write -Memory Execute Cycle (BSA) BSA X - Branch and save address Address of instruction following BSA is saved in X Execution continues from X+1 Page 582 BSA X BSA X - Branch and save address Address of instruction following BSA is saved in X Execution continues from X+1 Memory n X n+1 X+1 Procedure X BSA X …… Ad(return) …… 返回地址 BSA –Fetch – T1 BSA –Fetch – T2 BSA –Fetch – T3 BSA –Fetch – T4 +1 BSA –Execute – T1 BSA –Execute – T2 BSA –Execute – T3 BSA –Execute – T4 Execute Cycle (BSA) BSA X ; t1: Ad(MBR) -MAR - X t2: (PC) -MBR t3: (MAR)- Memory -保护返回地址到 X 地址中 (MBR) -Memory write -Memory —t4: (MAR)+1 -PC - X+1 Problems Add R, X; (X)+(R)-R — direct addressing Add A,(X); ((X))+(R)-R —indirect addressing CALL X; — call X function, save return address on the top of stack Return; —from top of stack return to PC Topic Write down all Micro operations about the following instructions (1) ADD X,R ; (2) RETURN; (the return address is in the stack) Pentium Interrupt Processing(see page 448) When an INTR(可屏蔽中断 ) interrupt is generated , it must be accompanied on bus with the interrupt number for this interrupt. CPU can read the number in the interrupt cycle. Interrupt Cycle (see page 448) Must do (simplified ): 1.Acknowledgement to interrupt request device to get device number 2.Save (PSW ) break-point address on the Top-of-stack, (by the SP) 3.Get the ISR’s address from IVT, interrupt vector table contain add