计算机组织与结构课件全分单元Ch121章节幻灯片.pptVIP

下载本文档

0
0
约3.95千字
约 26页
2018-03-27 发布于广东
举报
版权申诉

计算机组织与结构课件全分单元Ch121章节幻灯片.ppt

1、有哪些信誉好的足球投注网站（book118）网站文档一经付费（服务费），不意味着购买了该文档的版权，仅供个人/单位学习、研究之用，不得用于商业用途，未经授权，严禁复制、发行、汇编、翻译或者网络传播等，侵权必究。。
2、本站所有内容均由合作方或网友上传，本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺！文档内容仅供研究参考，付费前请自行鉴别。如您付费，意味着您自己接受本站规则且自行承担风险，本站不退款、不进行额外附加服务；查看《如何避免下载的几个坑》。如果您已付费下载过本站文档，您可以点击这里二次下载。
3、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等，请点击“版权申诉”（推荐），也可以打举报电话：400-050-0827(电话支持时间：9:00-18:30)。
4、该文档为VIP文档，如果想要下载，成为VIP会员后，下载免费。
5、成为VIP后，下载本文档将扣除1次下载权益。下载后，不支持退款、换文档。如有疑问请联系我们。
6、成为VIP后，您将拥有八大权益，权益包括：VIP文档下载权益、阅读免打扰、文档格式转换、高级专利检索、专属身份标志、高级客服、多端互通、版权登记。
7、VIP文档为合作方或网友上传，每下载1次，网站将根据用户上传文档的质量评分、类型等，对文档贡献者给予高额补贴、流量扶持。如果你也想贡献VIP文档。上传文档

24 27 28 30 31 33 35 William Stallings Computer Organization and Architecture6th Edition Chapter 12 CPU Structure CPU结构和功能 and Function §12.1 CPU Organization CPU must do: Fetch instructions Interpret instructions(Decode) Fetch data Process data Write(Store) data Page 412 CPU With Systems Bus Page 413 CPU CPU Internal Structure Page 414 状态标志移位器求补器算术布尔逻辑 §12.2 Registers Organization CPU must have some working space (temporary storage) Called registers Number and function vary between processor designs Top level of memory hierarchy(Chapter4) —Registers in the top —Faster access time —greater cost per bit —smaller capacity Page 414 Page100 Chapter10 Registers in CPU perform two roles User Visible Registers Control Status Registers Page 414 1.User Visible Registers General Purpose —Mean that they can contain operand or address Data —e.g.Accumulator Address —e.g.Segment Condition Codes(in PSW) —Can not (usually) be set by programs Page 415 Several design issues (1) Whether to use completely GP registers or to specialize their use Make them general purpose Increase flexibility and programmer options Increase instruction size complexity Make them specialized Smaller (faster) instructions Less flexibility Page 415 (2)How Many GP Registers? Between 8 - 32 Fewer = more memory references See also RISC (3)How length? Large enough to hold full address Large enough to hold full word 32bits 2. Control Status Registers Most of these are not visible , not operational to the user Four registers are essential to instruction execution： —Program Counter(PC) —Instruction Register(IR) —Memory Address Register(MAR) —Memory Buffer Register(MBR) Revision: what do these all do? ( See page 416 ) Page 416 Program Status Word(PSW) A set of bits Includes Condition Codes Sign of last result Zero Carry Equal Overflow Interrupt enable/disable Supervisor(管理 ):Indicates whether CPU is executing in s