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有限状态机设
when st1 = case data_in is when 00 = next_state = st0; when 10 = next_state = st2; when others = next_state = st1; end case; when st2 = case data_in is when 00 = next_state = st1; when 01 = next_state = st1; when 10 = next_state = st3; when 11 = next_state = st3; when others = null; end case; when st4 = case data_in is when 10 = data_out = 1; when 11 = data_out = 1; when others = data_out = 0; end case; when others = data_out = 0; end case; end process outputs; end behave; END CASE; END IF; END PROCESS; END behav; 1、数字表的晶振频率CP多为32768Hz，用16位串行二进制计数器计数分频可以得到1秒脉冲Q，如下图，要求： 1、写出描述J-K触发器的VHDL程序，J、K悬空为高电平。 2、写出用GENERATE语句和元件例化语句描述下面16位串行二进制计数分频器顶层的VHDL程序，输入CP，输出Q。 3、写出秒计数的异步60进制计数器的VHDL程序，D1、D2分别为4位和3位二进制输出（8421码），y为进位输出。 when st3 = case data_in is when 01 = next_state = st4; when 11 = next_state = st4; when others = next_state = st3; end case; when st4 = case data_in is when 11 = next_state = st4; when others = next_state = st0; end case; when others = next_state = st0; end case; end process fsm; outputs: process (pres_state, data_in) begin case pres_state is when st0 = case data_in is when 00 = data_out = 0; when others = data_out = 1; end case; when st1 = data_out = 0; when st2 = case data_in is when 00 = data_out = 0; when 01 = data_out = 0; when others = data_out = 1; end case; when st3 = data_out = 1; 根据状态图，写出对应结构的状态机 画出下面FSM的状态图和结构图 ?? entity?test?is?? ??port(?? ????sw?:in?std_logic_vector(3?downto?0);?? ????clk,reset???:in?std_logic;?? ????led???:out?std_logic_vector(3?downto?0));?? end?test;?? architecture?rtl?of?test?is?? ??type?state?is?(idle,s1,s2,s3);?? ??signal?tmp?:state;?? begin?? ??process(clk,reset)?? ??begin?? ????if?reset=0?then??tmp=idle;?? ????elsif?clkevent?and?clk=1?then?????? ??????case?tmp?is?? ??????when?idle?=?? ????????if?sw(1)=1?then???tmp=s1;?? ???????? else???tmp=idle;?? ???end?if;?? when?s1?=?? ????????if?sw(2)=1?then?? ??????????tmp=s2;?? ????????else?? ??????????tmp=idle;?? ????????end?if;?? ??????when?s2?=?? ????????i
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