EDA状态机的设计.docVIP

EDA实验报告 学院： 班级： 学号： 指导老师： 课程名称：状态机的设计 实验目的：加深对状态机设计的理解及应用，比较moore型和mealy型状态机的不同。 实验内容 mealy型状态机的设计 程序文本输入： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY S_MACHINE IS PORT ( CLK,RESET, STATE_INPUT :IN STD_LOGIC; COMB_OUTPUT : OUT STD_LOGIC ); END S_MACHINE; ARCHITECTURE BEHV OF S_MACHINE IS TYPE FSM_ST IS (idle, first_one, second_one, third_one); SIGNAL CURRENT_STATE, NEXT_STATE: FSM_ST; BEGIN REG: PROCESS (RESET,CLK) BEGIN IF RESET = 1 THEN CURRENT_STATE = idle; ELSIF CLK=1 AND CLKEVENT THEN CURRENT_STATE = NEXT_STATE; END IF; END PROCESS; COM:PROCESS(CURRENT_STATE, STATE_INPUT) BEGIN CASE CURRENT_STATE IS WHEN idle = IF STATE_INPUT = 0 THEN NEXT_STATE=idle;COMB_OUTPUT= 0; ELSE NEXT_STATE=first_one;COMB_OUTPUT= 0; END IF; WHEN first_one = IF STATE_INPUT = 0 THEN NEXT_STATE=idle;COMB_OUTPUT= 0; ELSE NEXT_STATE=second_one; COMB_OUTPUT= 0; END IF; WHEN second_one = IF STATE_INPUT = 0 THEN NEXT_STATE = idle; COMB_OUTPUT= 0; ELSE NEXT_STATE = third_one;COMB_OUTPUT= 1; END IF; WHEN third_one = IF STATE_INPUT = 0 THEN NEXT_STATE = idle; COMB_OUTPUT= 0; ELSE