实验二 加法器的设计与仿真 小强.docVIP

09级计科2班 20090810225 吴瑨强 实验 加法器的设计与仿真 实验内容 1．用VHDL语言设计全加器 2．利用设计的全加器组成串行加法器 3．用VHDL语言设计并行加法器。 全加器 library ieee; use ieee.std_logic_1164.all; entity f_adder is port( x,y,cin: in std_logic; s,cout: out std_logic ); end f_adder; architecture bhv of f_adder is begin s=x xor y xor cin; cout=(x and y)or(x and cin)or(y and cin); end bhv; 四位串行加法器 library ieee; use ieee.std_logic_1164.all; entity ffadder is port(x,y: in std_logic_vector(3 downto 0); cin: in std_logic; s: out std_logic_vector(3 downto 0); cout: out std_logic ); end ffadder; architecture bhv of ffadder is signal out1,out2,out3: std_logic; component f_adder is port(x,y,cin: in std_logic; s,cout: out std_logic ); end component f_adder; begin u1: f_adder port map(x(0),y(0),cin,s(0),out1); u2: f_adder port map(x(1),y(1),out1,s(1),out2); u3: f_adder port map(x(2),y(2),out2,s(2),out3); u4: f_adder port map(x(3),y(3),out3,s(3),cout); end bhv; 74283：4位先行进位全加器（4-Bit Full Adder） library ieee; use ieee.std_logic_1164.all; entity fulladder is port(x,y: in std_logic_vector(3 downto 0); cin: in std_logic; s: out std_logic_vector(3 downto 0); cout: out std_logic ); end fulladder; architecture bhv of fulladder is signal c: std_logic_vector(4 downto 0); signal g,p: std_logic_vector(3 downto 0); begin g(0)=x(0) and y(0); g(1)=x(1) and y(1); g(2)=x(2) and y(2); g(3)=x(3) and y(3); p(0)=x(0) or y(0); p(1)=x(1) or y(1); p(2)=x(2) or y(2); p(3)=x(3) or y(3); c(0)=cin; c(1)=g(0) or (p(0) and c(0)); c(2)=g(1) or (p(1) and g(0)) or (p(1) and p(0) and c(0)); c(3)=g(2) or (p(2) and g(1)) or (p(2) and p(1) and g(0)) or (p(2) and p(1) and p(0) and c(0)); c(4)=g(3) or (p(3) and g(2)) or (p(3) and p(2) and g(1)) or (p(3) and p(2) and p(1) and g(0)) or (p(3) and p(2) and p(1) and p(0) and c(0)); s(0)=x(0) xor y(0) xor c(0); s(1)=x(1) xor y(1) xor c(1); s(2)=x(2) xor