译码器程序.pptVIP

习 题 课 一 习题课2 * * library ieee; use ieee.std_logic_1164.all; entity Decoder1 is port(A: in std_logic_vector(2 downto 0); Y: out std_logic_vector(7 downto 0)); end Decoder1; architecture one of Decoder1 is begin process(A) begin 【3.3】3线-8线译码器的设计方法1（IF语句） if A=B000 then Y= elsif A=B001 then Y= elsif A=B010 then Y= elsif A=B011 then Y= elsif A=B100 then Y= elsif A=B101 then Y= elsif A=B110 then Y= elsif A=B111 then Y= else Y= end if; end process; End ; library ieee; use ieee.std_logic_1164.all; entity Decoder1 is port(A: in std_logic_vector(2 downto 0); Y: out std_logic_vector(7 downto 0)); end Decoder1; architecture one of Decoder1 is begin process(A) begin 【3.3】3线-8线译码器的设计方法2（CASE语句） case A is when 000 =Y when 001 =Y when 010 =Y when 011 =Y when 100 =Y when 101 =Y when 110 =Y when 111 =Y when others =Y end case; end process; end one; 【3.6】写出8D锁存器的实体 entity latch8 is port( D: in std_logic_vector(7 downto 0); CLK , OE: in std_logic; Q: out std_logic_vector(7 downto 0)); end latch8; 【3.9】找出错误 ARCHITECTURE one OF com1 IS signal clock: std_logic; BEGIN Pro1: PROCESS(clock) VARIABLE a,b,c: STD_LOGIC; BEGIN IF clock’EVENT and clock=‘0’ THEN x=(a xor b) or c; END IF; END PROCESS; END; next1= 1101 when a=0 and b=1 else d when a=0 else c when b=1