VHDL与Verilog HDL的对比以及三中建模方式.docxVIP

本文将以二选一多路器为例，分别用Verilog HDL和VHDL描述电路。二选一多路器的门级结构：HDL建模时，除了可以用不同层次的基本描述方式建模外，还可以根据七对信号描述方式的不同划分为三种：数据流建模，行为建模，结构化建模；在模块中对信号资源分配（或组合逻辑的连接）的描述称为数据流描述或数据流建模。在模块中对信号的行为进行描述，称为行为描述或行为建模。将特定功能的模块组织成更大的模块，其描述方式称为结构化描述或结构化建模。下面是用VHDL描述的二选一多路器，采用数据流建模方式。library ieee;use ieee.std_logic_1164.all;entity mux_dataflow isport(a:instd_logic;b:in std_logic;sel: in std_logic;c:out std_logic);end mux_dataflow;architecture dataflow of mux_dataflow isbeginc=(a and not sel) or (b and sel);end dataflow;下面是用Verilog HDL描述的二选一多路器，采用数据流建模方式。module mux_dataflow (a,b,sel,c);input a,b,sel;output c;wire c;assign c= (a ~sel) | (b sel);endmodule下面是用VHDL的行为建模方式描述二选一多路器。library ieee;use ieee.std_logic_1164.all;entity mux_behaviour isport(a: in std_logic;b: in std_logic;sel:in std_logic;c : out std_logic);end mux_behaviour;architecture behaviour of mux_behaviour is begin mux_process: process (a,b,sel)beginc=(a and not sel) or (b and sel);end process ;end behaviour;下面是用Verilog HDL描述的二选一多路器，采用行为建模方式。module mux_behaviour(a,b,sel,c);input a,b,sel;output c;reg c;always @(a,b,sel)beginc= (a ~sel) |(bsel);endendmodule虽然表达式几乎相同，但是他们有本质的不同。数据流建模方式侧重于信号怎么做。行为建模方式侧重于信号做什么。下面是用VHDL描述的二选一多路器，采用结构体建模方式。library ieee;use ieee.std_logic_1164.all;entity mux_structure is port(a : in std_logic;b : in std_logic;sel : in std_logic;c : out std_logic);end mux_structure;architecture structure of mux_structure is component and_gateport(a : in std_logic;b : in std_logic;c : out std_logic); end component;component or_gateport(a : in std_logic;b : in std_logic;c : out std_logic); end component;component inverterport(a : in std_logic;c : out std_logic); end component;signal x0,x1,x2 : std_logic;beginu0 : inverter port map(a = sel, c = x0);u1 : and_gate port map(a = b, b = sel, c = x1);u2 : and_gate port map(a = x0, b = a, c = x2);u3 : or_gate port map(a = x1, b = x2, c = c);end structure;---------------------and_gate-----------------------library ieee;use ieee.std_logic_1164.all;entity and_gate is port(a : in std_logic;b : in s