EDA-课件（PPT-精）.ppt

第1次课 第3次课 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DFF1 IS PORT (clk:IN STD_LOGIC; d:IN STD_LOGIC; q:OUT STD_LOGIC); END DFF1 ; ARCHITECTURE bhv OF DFF1 IS SIGNAL q1:STD_LOGIC; BEGIN PROCESS(clk) BEGIN IF clkEVENT AND CLK=1 THEN q1=D; END IF; q=q1; END PROCESS; END bhv; LIBRARY IEEE； USE IEEE.STD LOGIC 1164.ALL； ENTITY h_adder2 IS PORT（ a，b：IN STD LOGIC； so，co：OUT STD LOGIC）； END h_adder2 ； ARCHITECTURE fh2 OF h_adder2 IS SIGNAL sel:STD_LOGIC_VECTOR(1 DOWNTO 0); BEGIN sel=ab; PROCESS(sel) BEGIN CASE sel IS WHEN 00=so=0;co=0; WHEN 01=so=1;co=0; WHEN 10=so=1;co=0; WHEN 11=so=1;co=1; WHEN OTHERS=NULL; END CASE; END PROCESS; END fh2; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY or2a IS PORT (a,b:IN STD_LOGIC; c:OUT STD_LOGIC); END or2a; ARCHITECTURE one OF or2a IS BEGIN c=a OR b; END one; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY f_adder IS PORT (ain,bin,cin:IN STD_LOGIC; cout,sum :OUT STD_LOGIC); END ENTITY f_adder; ARCHITECTURE fd1 OF f_adder IS COMPONENT h_adder1 PORT(a,b: IN STD_LOGIC; co,so:OUT STD_LOGIC); END COMPONENT; COMPONENT or2a PORT(a,b: IN STD_LOGIC; c:OUT STD_LOGIC); END COMPONENT; SIGNAL d,e,f:STD_LOGIC; BEGIN u1: h_adder PORT MAP(a=ain,b=bin,co=d,so=e); u2: h_adder PORT MAP(a=e,b=cin,co=f,so=sum); u3: or2a PORT MAP(a=d,b=f,c=cout); END fd1; 第5次课 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY eqcomp4 IS PORT(a,b: IN STD_LOGIC_VECTOR(3 DOWNTO 0); equals: OUT STD_LOGIC); END eqcomp4; ARCHITECTURE behave OF eqcomp4 IS BEGIN comp:PROCESS(a,b) BEGIN equals=0; IF a=b THEN equals=1; END IF; END PROCESS comp; END behave; LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY eqcomp4 IS PORT(a,b: IN STD_LOGIC_VECTOR(3 DOWNTO 0); equals: OUT STD_LOGIC); END eqcomp4; ARCHITECTURE behave OF eqcomp4 IS BEGIN comp:PROCESS(a,b) BEGIN IF a=b THEN equals=1; ELSE equals=0;