AVR教程 AVR Architecture.pptVIP

December 2004 Architecture Core and Peripherals The AVR CORE Harvard architecture Separate memories and buses for program and data 32x8-bit general purpose working registers Large Accumulator Single clock cycle access time 3 register pair act as 16-bit data pointers Single-cycle Arithmetic Logic Unit (ALU) operation 16-bit Stack Pointer 22-bit Program Counter 32x8-bit General Purpose Registers 32 8-bit Accumulator Registers All have direct access to ALU 3 register pair act as 16-bit data pointers Instruction set support for auto increment, decrement and displacement of pointers Enabling efficient address calculations. Z Pointer suited for look up tables and indirect jump Direct address of up to 64K Single Cycle Instruction Execution Memory Overview and Interconnection General purpose registers manage all data transfer Direct Program memory access Direct SRAM access EEPROM access via IO registers EEAR,EEDR,EECR Secure Program memory and EEPROM access Timed sequence Program Memory and Data Pointers Stack Pointer + Three Data pointers One or two pointers + SP is common for 8-bit Pointer reloading is minimized Code efficient memory to memory copy Separate stacks for return addresses and local variables Pointer handling similar to C- language Auto Increment/Decrement Indirect with Displacement Efficient for accessing arrays and structs Efficient when placing local variables on Software Stack AVR - Designed for C Programming Architecture and instruction set co-designed with IAR Systems Compiler development project initiated before architecture and instruction set frozen Compiler experts’ advice implemented in hardware Potential HLL bottlenecks identified and removed The design process resulted in Instruction set support for 16-bit arithmetic operations 32 working registers which eliminate move to and from SRAM Single Cycle execution A Small C Function Code Size and Execution Time MSP430 and AVR are running a close race But max speed