quartus ii 13 0 VHDL官方教程.pdfVIP

Quartus® II Introduction for VHDL Users This tutorial presents an introduction to the Quartus® II software. It gives a general overview of a typical CAD flow for designing circuits that are implemented by using FPGA devices, and shows how this flow is realized in the Quartus® II software. The design process is illustrated by giving step-by-step instructions for using the Quartus® II software to implement a simple circuit in an Altera® FPGA device. The Quartus® II system includes full support for all of the popular methods of entering a description of the desired circuit into a CAD system. This tutorial makes use of the VHDL design entry method, in which the user specifies the desired circuit in the VHDL hardware description language. Another version of this tutorial is available that uses Verilog hardware description language. The screen captures in the tutorial were obtained using Quartus® II version 13.0; if other versions of the soft- ware are used, some of the images may be slightly different. Contents: Getting Started Starting a New Project Design Entry Using VHDL Code Compiling the VHDL Code Using the RTL Viewer Specifying Timing Constraints Quartus® II Windows Computer Aided Design (CAD) software makes it easy to implement a desired logic circuit by using a pro- grammable logic device, such as a field-programmable gate array (FPGA) chip. A typical FPGA CAD flow is illustrated in Figure 1. Figure 1: Typical CAD flow. It involves the following basic steps: • Design Entry – the desired circuit is specified either by using a hardware description language, such as Verilog or VHDL, or by means of a schematic diagram • Synthesis – the CAD Synthesis tool synthesizes the circuit into a netlist that gives the logic elements (LEs) needed to realize the circuit and the connections between the LEs • Func