10Gbit_sCMOS高增益限幅放大器的设计.pdfVIP

第32 卷 第1 期 电 子 器 件 V ol. 32 No. 1 2009 年2 月 Chinese Journal Of Elect ron Dev ices Feb. 2009 Design of a 10 Gbit/ s CMOS High Gain Limiting Amplifier * CH EN Zhun, FEN G Jun (I nstitute of R F- OE-I Cs , Southeast University , N anj in 210096, Ch ina) Abstract:A 10 Gbit/ s CMOS high gain limiting amplifier is designed in U MC 0. 13 Lm CM OS te hnology. In proposed design five stages of modified Cherry-Hooper onfigur ation is employed to in rease the gain- bandw idth produ t and tw o stages of output buffer to de rease the rise and fall time. T he post simulation show s the pow er dissipation is 70. 8 mW w ith the supply voltage of 1. 2 V. The limiting amplifier has pp a hieved a gain of 58. 7 dB and a - 3 dB bandw idth of 9 GHz. A n input dynami r ang is 46 dB( 6 mV ~ 1 200 mVpp ) w ith onstant output sw ing 600 mVpp . The rise and fall time( 10%~ 90% ) is 29 ps. T he ore ar ea is only 285. 8 Lm @ 148. 9 Lm and the hip die area is 665. 3 Lm @ 5 15. 3 Lm. Key ords:opti al fiber ommuni ation; limiting amplifier; Cherry-Hooper ar hite ture; rise and fall time; 0. 13 Lm CMOS te hnology EEACC:2570D 10 Gbit/ s CMOS * 陈 准, 冯 军 ( , 2 10096) : UMC 0. 13 Lm CMOS 10 Gbit/ s CMOS Cherry- Hooper , , 1. 2 V , 70. 8 mW , 58. 7 dB 9 GH z - 3 dB 46 dB( 6 mV ~ 1 200 pp mV ) , 600 mVpp, ( 10% ~ 90% ) 29 ps285. 8 Lm @ 148. 9 Lm, pp 665. 3 Lm @ 5 15. 3 Lm : ; ; Cherry-H ooper ; ; 0. 13 Lm CMOS :TN929. 11