一种自动变模控制的宽频带全数字锁相环.pdfVIP

∀#2009 20 307 一种自动变模控制的宽频带全数字锁相环 朱立军, 单长虹, 李 勇 ( 421001) : 针对传统的全数字锁相环只能锁定已知信号和锁频范围较 的问题, 提出了一种自动变模控制的宽频带全数 字锁相环对比分析了各类全数字锁相环锁频锁相的工作机理, 提出了一种新的系统模型, 重点研究了快速锁定和频带拓 宽的原理及实现方法应用EDA 技术完成系统设计, 并进行计算机仿真仿真结果证实了该设计具有快的锁定速度宽的 锁频范围并能快速跟踪频率突变的输入信号该锁相环通用性强, 易于集成, 可作为IP 核用于SoC 的设计 : 全数字锁相环; 鉴频器; 自动变模; 宽频带 :T N402 : A : 1004- 373X( 2009) 20- 011- 03 Automatic Modulus Controlled All Digital Phase Locked Loop with Large Lock- in Range ZH U Liju , SH AN Cha gho g, LI Yo g ( College of Electro ic E gi eeri g, Na hua U iversity, He gya g, 421001, Chi a) Abstract: A automatic modulus co trolled all digital phase locked loop with large lock- i ra ge is proposed for solvi g problems that the traditio al ADPLL o ly ca lock a k ow sig al a d lock- i ra ge is arrow. By compari g a d a alysi g all sorts of fre que cy a d phase locki g mechi aisims respectively show i differe t co ve tio al all digital phase- locked loop systems, a ovel sys tem model is proposed. The pri ciple a d method of impleme tatio about fast locked a d wide ba dwith are i troduced emphasely. The whole system is desig ed by usi g EDA tech ology, a d simulated by usi g computer. It makes sure from the simulatio results that the desig method has fast phase- locked speed a d w ide freque cy- locked ra ge, a d the phase locked loop ca track the i put sig al quckly w he a jump of the i put sig al freque cy occurs. The PLL is characteristic of excelle t adpatio , it is pro e to system i tegratio a d thus ca be packed as a IP core for SoC applicatio . Keyw ords: all digital phase locked loop; freque cy detector; automat ic modulus co trol; large lock- i ra g , , , [ 1, 2] ,