两位二进制加法.docVIP

半加器 1 library ieee; use ieee.std_logic_1164.all; entity h_adder is port(a,b:in std_logic; so,co:out std_logic);--so为和，co为低位向高位的进位 end h_adder; architecture fh1 of h_adder is begin so=a xor b;co=a and b; end architecture; 或门 library ieee; use ieee.std_logic_1164.all; entity or22 is port(a,b:in std_logic; c:out std_logic); 2 end or22; architecture one of or22 is begin c=a or b; end architecture; 一位全加器 library ieee; use ieee.std_logic_1164.all; entity f_adder is port(ain,bin,cin:in std_logic; cout,sum:out std_logic);--sum为和，cout为低位向高位的进位 end f_adder; architecture fd1 of f_adder is component h_adder port(a,b:in std_logic; so,co:out std_logic); end component; component or22 3 port(a,b:in std_logic; c:out std_logic); end component; signal d,e,f:std_logic; begin u1:h_adder port map(ain,bin,e,d); u2:h_adder port map(e,cin,sum,f);--sum he u3:or22 port map(a=d,b=f,c=cout); end fd1; 两位二进制全加器 library ieee; use ieee.std_logic_1164.all; entity erwei_adder is port(a,b:in std_logic_vector(1 downto 0); 4 ci:in std_logic; s:out std_logic_vector(1 downto 0); co:out std_logic); end erwei_adder; architecture quan of erwei_adder is component f_adder port(ain,bin,cin:in std_logic; cout,sum:out std_logic); end component; signal m:std_logic; begin v1: f_adder port map(a(0),b(0),ci,m,s(0)); v2: f_adder port map(a(1),b(1),m,co,s(1)); end quan; 并置 5 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY bingzhi IS PORT (a:IN STD_LOGIC_VECTOR(1 DOWNTO 0); b:in STD_LOGIC; c: out STD_LOGIC_VECTOR(2 DOWNTO 0)); END bingzhi; ARCHITECTURE behav OF bingzhi is BEGIN c=ba; end behav; 译码 6 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY yima IS PORT (shuru :IN