MIPS Lecture 1 - 上海交通大学ACM班.PDFVIP

MIPS Lecture 1 Liuli Chen Mar 2, 2012 Course Overview • What will you do? – simulate a MIPS CPU • Pipeline • Cache • Advance module (or Simics) • What will you use? – Modelsim 6.5b SE – Verilog TAs • Diyi Yang （杨笛一） • Hongyu Zhu （朱虹宇） • Liuli Chen （陈旒俐） Schedule • 3.2: First lecture(Pipeline) • 3.25(tentative): Deadline for Pipeline Phase Second lecture(Cache) • 4.16(tentative): Deadline for Cache Phase Third lecture(Optional Module) • 5.8(tentative): Final submit • 5.15(tentative): Presentation • No Delay! MIPS architecture • What is MIPS? – Microprocessor without Interlocked Pipeline Stages – a reduced instruction set computer (RISC) instruction set architecture (ISA) Pipeline Main components Registers Memory Instructions Instructions(cont.) • See Green Card Instructions(example) Instructions(example) Instructions(example) Instructions(example) Single sycle CPU Cut them into stages IF – Instruction Fetch EXE – (EXEcution) ID – Instruction Decode MEM – (MEMory access) WB – (Write Back) baseline How pipeline works hazard • Structural dependency – Add hardwares – Compiler • Control dependency – Delayed branch – *Dynamic branch prediction • Data dependency – Compiler – Forwarding – Stall Delayed branch Ambiguity • In jal, the return address in $ra is PC+4 instead of PC+8 Data dependency Forwarding 3 kinds of forwardings • Forward ALU result from EXE stage to I