绍兴县夏履镇土地利用总体规划.ppt

The Memory HierarchySept 29, 2006 Topics Storage technologies and trends Locality of reference Caching in the memory hierarchy Random-Access Memory (RAM) Key features RAM is traditionally packaged as a chip. Basic storage unit is normally a cell (one bit per cell). Multiple RAM chips form a memory. Static RAM (SRAM) Each cell stores a bit with a four or six-transistor circuit. Retains value indefinitely, as long as it is kept powered. Relatively insensitive to electrical noise (EMI), radiation, etc. Faster and more expensive than DRAM. Dynamic RAM (DRAM) Each cell stores bit with a capacitor. One transistor is used for access Value must be refreshed every 10-100 ms. More sensitive to disturbances (EMI, radiation,…) than SRAM. Slower and cheaper than SRAM. SRAM vs DRAM Summary Conventional DRAM Organization d x w DRAM: dw total bits organized as d supercells of size w bits Reading DRAM Supercell (2,1) Step 1(a): Row access strobe (RAS) selects row 2. Reading DRAM Supercell (2,1) Step 2(a): Column access strobe (CAS) selects column 1. Memory Modules Enhanced DRAMs DRAM Cores with better interface logic and faster I/O : Synchronous DRAM (SDRAM) Uses a conventional clock signal instead of asynchronous control Double data-rate synchronous DRAM (DDR SDRAM) Double edge clocking sends two bits per cycle per pin RamBus? DRAM (RDRAM) Uses faster signaling over fewer wires (source directed clocking) with a Transaction oriented interface protocol Obsolete Technologies : Fast page mode DRAM (FPM DRAM) Allowed re-use of row-addresses Extended data out DRAM (EDO DRAM) Enhanced FPM DRAM with more closely spaced CAS signals. Video RAM (VRAM) Dual ported FPM DRAM with a second, concurrent, serial interface Extra functionality DRAMS (CDRAM, GDRAM) Added SRAM (CDRAM) and support for graphics operations (GDRAM) Nonvolatile Memories DRAM and SRAM are volatile memories Lose information if powered off. Nonvolatile memories retain value even if powered off Read-only memory (ROM): programme