74HC273PW,112,74HC273D,653,74HCT273N,652,74HC273N,652,74HC273D,652, 规格书,Datasheet 资料.pdfVIP

74HC273; 74HCT273 Octal D-type flip-flop with reset; positive-edge trigger Rev. 03 — 24 January 2006 Product data sheet 1. General description The 74HC273; 74HCT273 is a high-speed Si-gate CMOS device and is pin compatible with Low-power Schottky TTL (LSTTL). The 74HC273; 74HCT273 has eight edge-triggered, D-type flip-flops with individual D inputs and Q outputs. The common clock (pin CP) and master reset (pin MR) inputs load and reset (clear) all flip-flops simultaneously. The state of each D input, one set-up time before the LOW-to-HIGH clock transition, is transferred to the corresponding output (Qn) of the flip-flop. All outputs will be forced LOW independently of clock or data inputs by a LOW voltage level on the MR input. The device is useful for applications where the true output only is required and the clock and master reset are common to all storage elements. 2. Features Ideal buffer for MOS microprocessor or memory Common clock and master reset Eight positive edge-triggered D-type flip-flops Complies with JEDEC standard no. 7A ESD protection: HBM EIA/JESD22-A114-C exceeds 2000 V MM EIA/JESD22-A115-A exceeds 200 V Multiple package options Specified from −40 °C to +85 °C and from −40 °C to +125 °C 3. Quick reference data Table 1: Quick reference data