用FPGA实现SMPTE协议,292M,259M等.pptVIP

Agenda Images to Video Basic Video Signals Progressive vs. Interlaced Color Space YCbCr Sampling Formats Agenda Broadcast / Pro. Video Standards Existing Standards Progressive Digital Vertical Timing Interlaced Digital Vertical Timing Parallel to Serial XYZ, LN, and CRC Agenda RX Pathological Signal Stress Testing (SDI Checkfield) Video Test Patterns SMPTE Color Bar Well known pattern for engineer to discern how an NTSC video signal has been altered 75% Color Bar The top row of the SMPTE Color Bar is a 75% color bar (75% intensity) . In this case, one replaces the lower portion of the SMPTE color bar with the 75% color bar. In some circumstances, 75% color bar is required, e.g. measurement of the HD-SDI output jitter Both have 16:9 aspect ratio 100% Color Bar Jitter Definitions TIMING JITTER (SD: 0.2UI, HD: 1.0UI) The variation in position of a signal’s transitions occurring at a rate greater than a specified frequency (10 Hz). ALIGNMENT JITTER (SD: 0.2UI, HD: 0.2UI) The variation in position of a signal’s transitions relative to those of a clock extracted from that signal. The bandwidth of the clock extraction process determines the low-frequency limit for alignment jitter Alignment jitter is the variation in the data transitions relative to a recovered clock, and timing jitter is the variation in the edge transitions of the recovered clock relative to a stable clock. Genlock Agenda Low Jitter Clocking Solutions- RX Support for automatic RX rate detection Rate Control Word Alignment only necessary when multi-rate operation is desired Low Jitter Clocking Solutions- TX Other existing FPGA devices also require jitter mitigation when connecting the recovered clock from the RX to the TX despite their higher cost. In above example, the jitter was attenuated by Gennum’s GS4915 when the asynchronous re-timing FIFO data read used a low jitter clock. LatticeECP2M Multi-rate IP Support The video pass-through demo has two modes: video pass-through mode and color bar