移位寄存器01587.docVIP

通过一个4位串入/并出移位寄存器设计过程来介绍如何设计串入/并出移位寄存器。 例程代码如下： LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL ; USE IEEE.STD_LOGIC_UNSIGNED.ALL ; ENTITY sipo IS PORT( D_IN :IN STD_LOGIC; CLK :IN STD_LOGIC; D_OUT :OUT STD_LOGIC_VECTOR(7 DOWNTO 0)); END sipo; ARCHITECTURE a OF sipo IS SIGNAL Q: STD_LOGIC_VECTOR(7 DOWNTO 0); BEGIN P1: PROCESS(CLK) BEGIN IF CLKEVENT AND CLK = 1 THEN Q(0) = D_IN; FOR I IN 1 TO 7 LOOP Q(I) = Q(I-1); END LOOP; END IF; END PROCESS P1; D_OUT =Q ; END a; 【例6-21】 用VHDL语言描述的8位串入-并出移位寄存器的示例程序。 (P215) LIBRARY IEEE ; USE IEEE.STD_LOGIC_1164.ALL ; ENTITY s_p_shift8 IS PORT ( shiftin : IN STD_LOGIC ; clk_pulse : IN STD_LOGIC ; Q : OUT STD_LOGIC_VECTOR ( 7 DOWNTO 0 ) shiftout : OUT STD_LOGIC ) ; END ENTITY s_p_shift8 ; ARCHITECTURE dataflow OF s_p_shift8 IS COMPONENT dff PORT ( d, clk : IN STD_LOGIC ; q : OUT STD_LOGIC ) ; END COMPONENT ; SIGNAL data_temp : STD_LOGIC_VECTOR ( 8 DOWNTO 0 ) ; BEGIN data_temp ( 0 ) = shiftin ; generate_inst : FOR i IN 0 TO 7 GENERATE dffn_x : dff PORT MAP ( data_temp ( i ), clk_pulse, Q ( i ) ) ; END GENERATE ; shiftout = data (8) ; END ARCHITECTURE dataflow ; 使用VHDL语言，设计一个8位并入/串出移位寄存器； library ieee; use ieee.std_logic_1164.all; entity piso is port( data_in: in std_logic_vector(7 downto 0); clk : in std_logic; nload: in std_logic; data_out: out std_logic); end piso; architecture func of piso is signal q: std_logic_vector(7 downto 0); begin process(nload,clk) begin if nload=0 then q=data_in; elsif clkevent and clk=1 then q(1)=q(0); for i in 1 to 7 loop q(i)=q(i-1); end loop; end if; end process; process(nload,clk) begin if nload=0 then data_out=0; elsif clkevent and clk=1 then data_out=q(7); end i