状态机和数据路径的详细阐述.pptVIP

6.4 状态机与数据路径;研究内容;有限状态机;Finite State Machine，FSM;有限状态机;为什么要使用状态机;nn;状态机分类;状态机状态;Mealy Machine;Moore Machine;状态机设计;状态机真值表;状态机仿真结果;两种综合结果比较;状态机描述风格;module fsm(clk,ina,out);input clk,ina;output out;reg out;parameter s0 = 3‘b00,s1 =3b01,s2 =3b10,s3=3b11;reg[0:1]state; always @ (posedge clk) begin state=s0; out =0; case(state) s0:begin state=(ina)?s1:s0; out=0; end s1:begin state=(ina)?s2:s0; out=0; end s2:begin state=(ina)?s3:s0; out=0; end s3:begin state=(ina)?s3:s0; out=1; end endcase endendmodule ;状态机编写风格;如果采用两个always来描述,程序的模块声明、端口定义和信号类型部分不变,只是改动逻辑功能描述部分,改动部分的程序如下： always @ (posedge dk) state_fsm =next_state; always @ (state_fsm or ina) begin state=s0;out =0; case(state_fsm ) s0: begin next_state=(ina)?s1:s0;out=0; end s1: begin next state=(ina)?s2:s0;out=0： end s2: begin next_state=(ina)?s3:s0;out=0; end s3: begin next_state=(ina)?s3:s0;out=1; end endcase end;状态机编写风格（Two always）;;状态机编写风格（three always）;综合结果比较;;;描述方法比较;状态机编码风格;;状态编码;状态编码;状态编码;可综合的FSM编码 ;;状态机设计流程;Example;Final State Transition Table;State Reduction;State Assignment;Coded State Transition Table;Problems;Corrected State Machine Design;Corrected State Transition Table;Improved Coded State Transition Table;module moore_bad(Clk, Reset, In_Data, Out_Data); input Clk, Reset, In_Data; output [1:0] Out_Data; reg [1:0] Out_Data; reg [1:0] State; parameter S0=2b00, S1=2b01, S2=2b11, S3=2b10; always @(posedge Clk) begin if(Reset) State=S0; else begin case(State) ;Note: only “State” is implemented with flip-flops) ;状态机设计准则 ;FSM输出方法;有限状态机HDL描述规则;可靠性与容错性;问题2