16.6 Methodology and Experimental Verification for Substrate Noise Reduction in CMOS Mixed-.pdfVIP

1 of 11 16.6 Methodology and Experimental Verification for Substrate Noise Reduction in CMOS Mixed-Signal ICs with Synchronous Digital Circuits Mustafa Badaroglu1,2, Marc van Heijningen1, Vincent Gravot1, John Compiet1, Stéphane Donnay1, Marc Engels1, Georges Gielen3, Hugo De Man1,3 1 IMEC, Leuven, Belgium 2 Also Ph.D. student at K.U. Leuven, Belgium 3 K.U. Leuven, Belgium Substrate noise degrades the performance of analog circuits integrated on the same substrate with digital circuits. In these mixed-signal ICs, the low cost and lower static power consumption of CMOS logic are shadowed by the larger noise generation due to the large rail-to-rail voltages and the sharp current spikes during switching. We have designed and measured a mixed-signal chip, fabricated in a 0.35μm CMOS process on an epi-type substrate, which allows us to compare several low-noise digital designs in CMOS. Alternative logic families have been proposed such as current-mode logic [1] or self-timed logic which show orders of magnitude noise reduction, however with increasing static power and delay sensitivity respectively. A few publications exist about low-noise digital CMOS design, e.g. CMOS gates with guard wiring and on-chip decoupling [2], where 67% noise reduction is achieved, but with considerable area penalty due to the additional circuitry and power rails. The test chip (Figure 16.6.1) contains one reference design (REF) and two digital low-noise designs (LN1, LN2) with the same basic architecture, shown in Figure 16.6.2. LN1 employs an optimized clock tree to make the supply current flatter and LN2 employs a separate substrate bias, dual-supply, and on-chip decoupling. REF has an area of 0.362mm2, a maximum speed of 45MHz and a core power consumption of 112mW at 42MHz and 3.3V. It is possible to disable the I/O pads in order to measure the substrate noise generation from the core logic only. In that case the input is generated by an on-chip 10-bit Pseudo Random Binary Sequencer (PRBS)