ESD Protection Solutions for High Voltage Technologies.pdfVIP

ESD Protection Solutions for High Voltage Technologies Bart Keppens (1), Markus P.J. Mergens (1), Cong Son Trinh (2), Christian C. Russ (3), Benjamin Van Camp (1), Koen G. Verhaege (1) (1) Sarnoff Europe, Brugse Baan 188A, B-8470 Gistel, Belgium, phone: +32-59-275-915; fax: +32-59-275-916; e-mail: bkeppens@ (2) Sarnoff Corporation, 201 Washington Road, Princeton, NJ-08543, USA (3) formerly Sarnoff Corp, now Infineon Technologies AG, Balanstrasse 73, D-81541 Munich, Germany Abstract - There is a trend to revive mature technologies while including high voltage options. ESD protection in those technologies is challenging due to narrow ESD design windows, NMOS degradation issues and the creation of unexpectedly weak parasitic devices. Different case studies are presented for ESD protection based on latch-up immune SCR devices. I. Introduction Many companies extend mature, less expensive CMOS technologies (0.35um and above) with new options and features such as high voltage (HV) or bipolar modules for instance for specific automotive or consumer electronics products. The strategy of technology upgrading offers significant economical advantages in this competitive market segment. For HV technology upgrades, HV MOS transistors are equipped with thick gate oxides and lowly doped drain/source implants to increase the voltage tolerance of the devices. This allows driving the maximum operating voltages to the limits of the process technology. ESD protection elements used in the HV domains need to be able to withstand these high voltages. However, the implant envelopes applied for HV compatibility dramatically degrade the high current behavior of conventional protection elements, such as ggNMOS transistors. In addition, other issues as for example weak parasitic current paths and high latch-up susceptibility are commonly observed. First, the paper reviews serious key issues commonly encountered for standard HV ESD transistors. The focus of