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()Introduction.ppt

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()Introduction

DSPx m Introduction DM643x One Day Workshop What is DaVinci? Technology? Outline Different Needs? Multiple Families. First Complete Video Platform TMD320DM6446: Arm + DSP TMS320DM644x in Production Now TMS320DM6437: DSP Only TMS320DM643x Sampling Now TMS320DM647/8: Multiple Video Ports TMS320DM647/8 C6000 CPU Architecture Challenge: Keeping 4800 MIPS CPU “Fed” DM643x Internal Memory C64x+ Improved Bandwidth Buses Internal to Megamodule Use of 256-bit buses Run at ? CPU rate to save on power CPU/DMA concurrency in L1D 256-bits available every cycles 8 x 32-bits 128-bits maximum requested by CPU 2 x 64-bit Paths to CPU 128 bits left over for DMA Each 32-bit bank arbitrated independently CPU/DMA concurrency in L2 CPU Access to L2 is infrequent over time In some chips, two distinct 128-bit pages arbitrated separately More DMA System Memory Connection compared to C64x 2 x busses. Dedicated buses for each Cache requests DMA’s into internal memory Upto 2 x width 128 bits wide DM643x EDMA 3.0 Enhanced Direct Memory Access Controller 3.0 (EDMA 3.0) Performs Data Transfers to offload DSP Transfer Controller (TC) Improvements over DM644x 3 Transfer Controllers (TC0, TC1, TC2) TC0: Short burst transfers with stringent deadlines (e.g. audio data) TC1: High throughput bulk transfers TC2: PCI or miscellaneous transfers Programmable Default Burst Size (DBS) for each TC System Module register EDMATCCFG Recommendation: Use default DBS Reference EDMA User’s Guide (SPRU987) Device-Specific Data Manual for details on EDMATCCFG register DM643x Switched Central Resource DM643x IDMA C64x+ IDMA Channel 1:Block Transfers between L1P, L1D, L2 One 256-bit accesses every other CPU cycle Programmation IDMA1_SOURCE, IDMA1_DEST: Transfer addresses. One end must be L1D/L2 other must be configuration space IDMA1_COUNT: Bytes to transfer Conclusion: Keeping 4800 MIPS CPU “Fed” Outline TMS320DM643x Software Overview Hardware Abstraction: EPSI and VISA Application Programming: EPSI API Applic