算术逻辑单元(ALU)设计.docVIP

LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; ENTITY alu IS PORT( sel,wt,cin,s2,s1,s0,clk :IN STD_LOGIC;--sel.wt选择输入AB，s2.s1.s0选择逻辑运算，clk时钟 din:IN STD_LOGIC_VECTOR(1 DOWNTO 0);--因为按键不够 将输入8位2进制通过din来分别 d:IN STD_LOGIC_VECTOR(3 DOWNTO 0); --输入din01时d置入低4位 din10时d置入高4位 dig:OUT STD_LOGIC_VECTOR(2 DOWNTO 0);--数码管位选 f:OUT STD_LOGIC_VECTOR(7 DOWNTO 0); ----数码管段位 cout:OUT STD_LOGIC); ---执行s2s1s0为100带进位加法时是否溢出 END alu; ARCHITECTURE behave OF alu IS SIGNAL z :STD_LOGIC_VECTOR(8 DOWNTO 0); ----s2s1s0为100时带进位加法结果暂存 SIGNAL s,scan :STD_LOGIC_VECTOR(2 DOWNTO 0);-- --scan是位选 s是逻辑运算指令暂存 SIGNAL rw :STD_LOGIC_VECTOR(1 DOWNTO 0); ----控制暂存AB信号 SIGNAL seg_r,f_r,d_r :STD_LOGIC_VECTOR(7 DOWNTO 0); ---d_r,f_r输入、结果输出暂存，seg_r数码管段位暂存 SIGNAL data_r :STD_LOGIC_VECTOR(3 DOWNTO 0); ----译码器输入暂存 begin process(sel,wt,d,din) variable a,b :STD_LOGIC_VECTOR(8 DOWNTO 0); begin rw=sel wt; s=s2s1s0; z=a+b+cin; f=seg_r; dig=scan; if clkevent and clk=1 then if(scan = 001) then scan = 000; else scan = scan + 1; end if; case din is when 01=d_r(3 downto 0)=d; when 10=d_r(7 downto 4)=d; when others=null; end case; case rw is when 10=a(7 downto 0):=d_r; when 01=b(7 downto 0):=d_r; when others=null; end case; case s is when 000=f_rcout=0;---清零 when 001=f_r=a(7 downto 0) and b(7 downto 0);cout=0;---逻辑乘 when 010=f_r=a(7 downto 0) or b(7 downto 0);cout=0;---逻辑加 when 011=f_r=a(7 downto 0) xor b(7 downto 0);cout=0;--逻辑异或 when 100=f_r=z(7 downto 0);cout=z(8);---带进位输入的算术加法 when 101=f_r=a(6 downto 0)0;cout=0;---A左移一位 when 110=f_r=0 a(7 downto 1);cout=0;---A右移一位 when others=null; end case; case scan is when 000 = data_r=f_r(7 downto 4); when 001 = data_r=f_r(3 downto 0); when others=null; end case; case data_r is when x0 = seg_r = x3f; when x1 = seg_r = x06; when x2 = seg_r = x5b; when x3 = seg_r = x4f; when x4 = seg_r = x66; when x5 = seg_r = x6d; when x6 = seg_r = x7d; when x7 = seg_r = x07; when x8 = seg_r = x7f; when x9 =