EDA_程序题..docVIP

2. 看下面原理图，写出相应VHDL描述 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MYCIR IS PORT (A, CLK : IN STD_LOGIC; C, B : OUT STD_LOGIC ); END MYCIR; ARCHITECTURE BEHAV OF MYCIR IS SIGNAL TA : STD_LOGIC; BEGIN PROCESS (A, CLK) BEGIN IF CLK’EVENT AND CLK = ‘1’ THEN TA = A; B = TA; C = A AND TA; END IF; END PROCESS; END BEHAV; 2. 看下面原理图，写出相应VHDL描述 Library ieee; Use ieee.std_logic_1164.all; Entity mycir is Port (ain , bin , clk : in std_logic; Cout : out std_logic); End mycir; Architecture one of mycir is Signal tb, tc; begin Process (clk) begin If clk’event and clk = ‘1’ then tb = bin; end if; End process; Process (clk, tc) begin If clk = ‘1’ then cout = tc;end if; End process; Tc = ain xor tb; End one; 1．设计一个3-8译码器 输入端口： din 输入端，位宽为3位 EN 译码器输出使能，高电平有效 输出端口： xout 译码器输出，低电平有效 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY DECODE3_8 IS PORT ( DIN : IN STD_LOGIC_VECTOR (2 DOWNTO 0); EN : IN STD_LOGIC; XOUT : OUT STD_LOGIC_VECTOR (7 DOWNTO 0)); END DECODE3_8; ARCHITECTURE ONE OF DECODE3_8 IS BEGIN PROCESS (DIN, EN) BEGIN IF EN = ‘1’ THEN IF DIN = “111” THEN XOUT = ; ELSIF DIN = “110” THEN XOUT = ; ELSIF DIN = “101” THEN XOUT = ; ELSIF DIN = “100” THEN XOUT = ; ELSIF DIN = “011” THEN XOUT = ; ELSIF DIN = “010” THEN XOUT = ; ELSIF DIN = “001” THEN XOUT = ; ELSE XOUT = ; END IF; END PROCESS; END ONE; 2. 看下面原理图，写出相应VHDL描述 LIBARRY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY MYCIR IS PORT ( XIN, CLK : IN STD_LOGIC; YOUT : OUT STD_LOGIC); END MYCIR; ARCHITECTURE ONE OF MYCIR IS SIGNAL A, B, C; BEGIN B = XIN OR A; PROCESS (CLK) BEGIN IF CLK’EVENT AND CLK = ‘1’ THEN A = C; C = B; END IF; END PROCESS; YOUT = C; END ONE; 根据原理图写出相应的VHDL程序：（10分） Library ieee; Use ieee.std_logic_1164.all; Entity mycir is Port ( A, B, clk : in std_logic; Qout : out std_l