硬體描述語言VerilogHDL.ppt

Digital IC Design Flow 2004.02.27 Huai-Yi Hsu Digital IC Design Flow Lecturer: Huai-Yi Hsu (許槐益) Date: 2004.02.27 Outline Introduction IC Design Flow Verilog History HDL concept Moore’s Law: Driving Technology Advances Logic capacity doubles per IC at regular intervals (1965). Logic capacity doubles per IC every 18 months (1975). Process Technology Evolution Chips Sizes Shrinking Product Cycles Shrinking product cycles Shrinking development turnaround times Need for productivity increase (remember the “design gap”) Design Productivity Crisis Human factors may limit design more than technology. Keys to solve the productivity crisis: Design techniques: hierarchical design, SoC design (IP reuse, platform-based design), etc. CAD: algorithms methodology Increasing Processing Power Very high performance circuits in today’s technologies. Gate delays: ~27ps for a 2-input Nand in CU11 Operating frequencies: up to 500MHz for SoC/Asic, over 1GHz for custom designs The increase in speed/performance of circuits allowed blocks to be reused without having to be redesigned and tuned for each application Enhanced Design Tools and Techniques Although not enough to close the “design gap”, tools are essential for the design of today’s high-performance chips IP-Based SoCs An Evolutionary Path Early days IP/Cores not really designed for reuse (no standard deliverables) Multiple Interfaces, difficult to integrate IPs evolved: parameterization, deliverables, verification, synthesizable On-Chip bus standards began to appear (e.g, IBM, ARM) Reusable IP + Common on-chip bus architectures 1998: max number of cores 30 cores  core content between 50% and 95% IP / Cores Soft Core Delivered as RTL verilog or VHDL source code with synthesis script (i.e: clock generation logic) Customers are responsible for synthesis, timing closure, and all front-end processing Firm Core Delivered as a netlist to be included in customer’s netlist (with dont touch attribute) Possibly with placement in