VHDL电路设计例代码.docVIP

【例-1】 LIBRARY IEEE; --IEEE库使用说明语句 USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux21 IS --实体说明部分 PORT( a,b : IN STD_LOGIC; s: IN STD_LOGIC; y: OUT STD_LOGIC ); END ENTITY mux21; ARCHITECTURE mux21a OF mux21 IS --结构体说明部分 BEGIN PROCESS(a,b,s) BEGIN IF s=0 THEN y=a; ELSE y=b; END IF; END PROCESS; END ARCHITECTURE mux21a; 【例-2】 ENTITY nand2 IS GENERIC ( t_rise : TIME := 2ns ; t_fall : TIME := 1ns ) PORT( a: IN BIT; b : IN BIT; s : OUT BIT); END ENTITY nand2; 【例-3】 ENTITY nand_n IS GENERIC ( n : INTEGER ) ; PORT( a : IN STD_LOGIC_VECTOR(n-1 DOWNTO 0); s : OUT STD_LOGIC ); END ENTITY nand_n; 例-4】 ENTITY half_adder IS PORT( x,y : IN BIT; s: IN BIT; c: OUT BIT); END ENTITY half_adder; ARCHITECTURE dataflow OF half_adder IS BEGIN s = x XOR y; c = x AND y; END ARCHITECTURE dataflow; 【例-5】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux21 IS PORT( a,b : IN STD_LOGIC; s: IN STD_LOGIC; y: OUT STD_LOGIC ); END ENTITY mux21; ARCHITECTURE behav OF mux21 IS BEGIN PROCESS(a,b,s) BEGIN IF s=0 THEN y=a; ELSE y=b; END IF; END PROCESS; END ARCHITECTURE behav; 【例-6】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY mux21 IS PORT( a,b : IN STD_LOGIC; s: IN STD_LOGIC; y: OUT STD_LOGIC ); END ENTITY mux21; ARCHITECTURE dataflow OF mux21 IS BEGIN y=(a AND (NOT s)) OR (b AND s); END ARCHITECTURE dataflow; 【例-7】 LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; ENTITY and21 IS PORT(i0,i1 : IN STD_LOGIC; q: OUT STD_LOGIC ); END ENTITY and21; ARCHITECTURE one OF and21 IS BEGIN q=i0 AND i1; END ARCHITECTURE o