基于FPGA的出租车计费器设计_.doc

基于FPGA的出租车计费器设计 目 录 TOC \o 1-3 \h \u =kinside:=0; --停止状态或空档 when001=kinside:=28; --第一档 when010=kinside:=24; --第二档 when011=kinside:=20; --第三档 when100=kinside:=16; --第四档 when101=kinside:=12; --第五档 when110=kinside:=8; --第六档 when111=kinside:=4; --第七档 end case; if reset=1then --复位清零 s_state:=s0; elsif clkevent and clk=1then --时钟上升沿到达时，状态转换 case s_state is when s0= cnt:=0; clkout=0; if start=1then s_state:=s1; else s_state:=s0; end if; when s1= clkout=0; if stop=1then s_state:=s0; --相当于无客上车 elsif sp=then s_state:=s1; --有客上车但车速为0，即刚上车还未起步 elsif cnt=kinside then cnt:=0; clkout=1; s_state:=s1; else cnt:=cnt+1; s_state:=s1; end if; end case; end if; end process; end rtl; Times模块 library ieee; --加载库文件 use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity times is port( --定义输入输出端口 clk :in std_logic; reset:in std_logic; start:in std_logic; stop :in std_logic; sp :in std_logic_vector(2 downto 0); timecount:out std_logic ); end times; architecture rtl of times is begin process(reset,clk,sp,stop,start) --启动进程 type state_type is(t0,t1,t2); variable t_state:state_type; variable waittime:integer range 0 to 1; begin if reset=1then --复位清零 t_state:=t0; elsif(clkevent and clk=1)then --时钟上升沿到达 case t_state is --根据条件完成状态转换 when t0= waittime:=0; timecount=0; if start=1then t_state:=t1; else t_state:=t0; end if; when t1= if sp=then t_state:=t2; else waittime:=0; t_state:=t1; end if; when t2= waittime:=waittime+1; --等待时间加1 timecount=0; if waittime=1 then timecount=1; --产生一个时间计费脉冲 waittime:=0; elsif stop=1then t_state:=t0; elsif sp=then t_state:=t2; else timecount=0; t_state:=t1; end if; end case; end i