一位半加器实验报告.docxVIP

实验一 1位半加器 实验目的 熟悉利用QuartusH的原理图输入方法设计简单组合电路，并掌握其设 计方法和软件的应用 实验原理： 1位半加器可以由与、或 非等基本门构成，如下图所示。 半加器的真值表中两个输入是加数A和B ,输出有一个是C ,另一个是D。 A B C D 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 实验内容 按半加器的原理图完成输入、编译，然后进行仿真。 四、 步骤 1、 项目的新建 New Project Wizard： Directory^ Ns匕 Top-Lvtl Entity [pt(? 1 of 5] Whdt i$ the wockng (ireclory for thk protect? [CA￡BB What i$ the name of thi$ ccoject? What is the name of the top level design entity few this p(oiect? This name is ca$e senskive and must exactly match the entity name in the design fileyuaryuanUse Existing Project Settings What is the name of the top level design entity few this p(oiect? This name is ca$e senskive and must exactly match the entity name in the design file yuaryuan Use Existing Project Settings …| —旦 —旦 New Pr oj ect Wi zrd： Family dl Devi ce Set t i ns [pae 3 o￡ 5J Select the family and device you want to target foe completion Eamily: T ar get device L Auto device selected by the Fitter from the Available devices fist G Specific device selected in Available devices* 3 Edckage:|AnyPin count:|AnySpeed ycade: Edckage: |Any Pin count: |Any Speed ycade: |Any Coe voltage 5 CM Filters Q Show Advanced Devices Available dewco$: EPM7064STC44-5 EPM7064STC446 EPM7064STC44-7 EPM7064STI44 7 EPM7064STC44-10 EPM7064STC100-5 EPM7064STC100-6 EPM7064STC100-7 E PM 7064ST1100-7 E PM 7064S TCI 00-10 EPM7128SLC84-6 EPM7128SLC847 tHM/128SLU84-1U EP)Mm^28SU^10 rFPM7i2^nr7inrbA Bck [ N.xt [ Fini sh 2、 半加器的原理图设计 倒 K/wyy/ywanjwanbd 3、 编译 Flow Status Flow Status Quartus II Version Revision Top-1 tvel Entity Nm? PMily Devic* Successful - Mon Nov 26 12:52:31 2012 5.0 Build 148 04/26/2005 SJ Full Vtrxion yutnyutn yuanyuan MAX7000S EPB7128S1JC84-15 Quartus II Full Co?pilttion was successful (0 errors, 0 warnings) 4、 仿真 仿真要设置仿真结束时间,波形编辑器默认的仿真结束时间为WS ,根据仿真需 要,可以自由设置仿真的结束时间。选择QUARTUSII软件的EditEnd Timo命令, 弹出线路束时间对话框,在Timo框办输入仿真结束时间,点击0K按钮完成设置。 5、仿真结果 lister Iiu Iff 21.15 m jjfoiittr： M u httml： ?1.06 m Start： 1 bi 实验心得 通过本次实验，我进一步熟悉了 Quartusiis. 0软件的使用，并进一步学习