基于TDC的全数字锁相环研究与设计-集成电路工程专业论文.docxVIP

Abstract With the rapid development of integrated circuits, a PLL (Phase-Locked Loop) has played an important role in VLSI circuits as an important part of modern clock generation circuits, which is used to provide on-chip high-speed clocks.Based on reading a large number of domestic and foreign literature on phase-locked loop technologies, we firstly introduce the development, concept, classification and application of PLL, and deeply analyse the structural principle of All-Digital PLL. Then the ADPLL (All-Digital PLL) with TDC (Time to Digital Converter) is designed in this paper. In this paper, the ADPLL’s system structure, sub-circuit blocks, and mathematical model are proposed, and its stability and viability are analyzed. Among them, the traditional TDC is improved by adding the circuit of rising edge detection and expanding the width of counter, which not only achieves the basic function, but also improves the accuracy and the measurement range of the TDC. A FRO’s (Free-running Ring Oscillator) outputs offer a multi-phase reference signal for the DCO (Digital-Controlled Oscillator) and TDC, so the product of convention resolution is fixed to 1. It not only makes the system more stable and reliable, but also be insensitive to the number of modules to process, voltage and temperature. Adding the programmable arbitrary integer divider, the feedback clocks waveform duty cycle is fifty percent. Simplifying the structure of the traditional DCO, the basic functions remain unchanged, and the circuit area is effectively reduced. Furthermore, this paper focuses on introducing the design method and programming skills of all of digital circuits, the digital integrated circuit design flow and mixed analog-digital simulation process. Based on standard 0.18μm CMOS technology, the proposed ADPLL’s RTL-level modeling, simulation and the key module’s layout are implemented using the top-down design method. Simulation results show that the output frequency range from 64 MHz to