毕业设计（论文）-基于PGA的数字频率计的设计.docxVIP

PAGE \* MERGEFORMAT 23摘 要 EDA 技术的发展，改变了传统的电子设计方法。FPGA 等大规模可编程逻辑器件的广泛应用，使电子设计变得和软件编程一样方便快捷。电子设计技术的进步，也改变了传统频率计的设计方法。常用的频率测量方法既有模拟的利用电路频率特性测量频率的方法，又有利用脉冲计数测量频率的数字方法。随着数字电路技术的发展，以脉冲计数法为基础衍生出各种改进型的数字测频方法，在测量精度、测量响应的快速性等方面都有了很大提高。简易数字频率计的设计，采用 FPGA实现对对外来信号采样，运用VHDL在FPG/CPLD器件上实现一种数字频率计测频系统，其在单位时间内通过计数器的累加实现对频率的计数。分析了数字频率计软件构成结构，并对其中的测频控制信号发生器电路进行了VHDL软件编程实现。该设计实现的频率精度为1Hz，测量范围为 0～100MHz，经实际电路测试，仿真结果表明，该频率计具有较高的实用性和可靠性。VHDL程序通过综合、适配后形成配置文件，下载到FPGA器件中对FPGA 进行配置，使 FPGA 成为实用的测频模块。通过modelsim波形仿真，符合本次设计的要求。最后，通过完整编译后的pof文件固化到开发板，接上高频信号源，实现了数字频率计的设计。关键词：数字频率计；频率测量；EDA；FPGA；VHDL 语言；配置器件AbstractDevelopment of EDA technology has changed the traditional electronic design methods. Widely used in large-scale FPGA and other programmable logic devices, electronic design and software programming becomes as easy and quick. Advances in electronic design technology, but also changed the traditional frequency meter design.Existing conventional frequency measurement method using analog frequency characteristics of the measured frequency of the circuit, but also the use of a digital pulse counting frequency measurement method. With the development of digital circuit technology to pulse count based on the law derived from a variety of improved digital frequency measurement method, measurement accuracy, fast response measurement and other aspects have been greatly improved.Simple digital frequency meter design, FPGA is used for foreign signal sampling, use VHDL to achieve a digital frequency meter frequency measurement system on the FPG / CPLD devices, which in unit time to achieve frequency counted by the counter accumulation. Analysis of the digital frequency meter software composition structure and one of the frequency measurement control signal generator circuit were VHDL software programming. Frequency accuracy of the design and implementation of 1Hz, measurement range is 0 ~ 100MHz, through the actual circuit test, simulation results show that the frequency meter with high availabil