EDA_VHDL语言程基本结构.ppt

第三章 VHDL编程基础 3.1 概述 3.2 VHDL程序基本结构 3.3 VHDL语言要素 3.4 VHDL顺序语句 3.5 VHDL并行语句 3.6 子程序 3.7 库、程序包及其他 3.8 VHDL描述风格 3.9 基本逻辑电路设计 3.10 状态机的VHDL设计 3.1 概述 3.1.1常用硬件描述语言简介 3.1.2VHDL的优点 3.1.3VHDL程序设计约定 3.1.1常用硬件描述语言简介 VHDL、Verilog和ABEL 三者的比较 （1）逻辑描述层次 （2）设计要求 （3）综合过程 （4）对综合器的要求 （5）支持的EDA工具 （6）VHDL的优点 3.1.2 VHDL的优点 Levels of design description Register Transfer Logic (RTL) Design Description Design process for FPGAs (1) Design process for FPGAs (2) 程序例子 全加器VHDL程序 3.1.3 VHDL程序设计约定 语句结构描述中方括号[]内的内容为可选内容 对于VHDL的编译器和综合器来说，程序文字的大小是不加区分的。 注释使用双横线-- 使用层次缩进格式，同层次对齐，低层次的，较高层次的缩进两个字符 建议各个源程序文件的命名与其实体名一致 Naming and Labeling (1) VHDL is not case sensitive Example: Names or labels databus Databus DataBus DATABUS are all equivalent Naming and Labeling (2) General rules of thumb (according to VHDL-87) All names should start with an alphabet character (a-z or A-Z) Use only alphabet characters (a-z or A-Z) digits (0-9) and underscore (_) Do not use any punctuation or reserved characters within a name (!, ?, ., , +, -, etc.) Do not use two or more consecutive underscore characters (__) within a name (e.g., Sel__A is invalid) All names and labels in a given entity and architecture must be unique Free Format VHDL is a “free format” language No formatting conventions, such as spacing or indentation imposed by VHDL compilers. Space and carriage return treated the same way. Example: if (a=b) then or if (a=b) then or if (a = b) then are all equivalent Readability standards  Consistent Writing Style Consistent Naming Conventions Consistent Indentation Consistent Commenting Style Recommended File Headers File naming and contents Number of statements/declarations per line Ordering of port and signal declarations Constructs to avoid Comments Comments in VHDL are indicated with a “double dash”, i.e., “--” Comment indicator can be placed anywhere in the line Any text that follows in the same line is treated as a comment Carriage return terminates a comment No method for commenting a block e