Exponentiator Sub-Threshold Design - Harvey Mudd College乘幂运算器的亚阈值设计哈维玛德学院.pptVIP

下载本文档

5
0
约4.37千字
约 28页
2018-06-24 发布于四川
举报
版权申诉

Exponentiator Sub-Threshold Design - Harvey Mudd College乘幂运算器的亚阈值设计哈维玛德学院.ppt

1、有哪些信誉好的足球投注网站（book118）网站文档一经付费（服务费），不意味着购买了该文档的版权，仅供个人/单位学习、研究之用，不得用于商业用途，未经授权，严禁复制、发行、汇编、翻译或者网络传播等，侵权必究。。
2、本站所有内容均由合作方或网友上传，本站不对文档的完整性、权威性及其观点立场正确性做任何保证或承诺！文档内容仅供研究参考，付费前请自行鉴别。如您付费，意味着您自己接受本站规则且自行承担风险，本站不退款、不进行额外附加服务；查看《如何避免下载的几个坑》。如果您已付费下载过本站文档，您可以点击这里二次下载。
3、如文档侵犯商业秘密、侵犯著作权、侵犯人身权等，请点击“版权申诉”（推荐），也可以打举报电话：400-050-0827(电话支持时间：9:00-18:30)。
4、该文档为VIP文档，如果想要下载，成为VIP会员后，下载免费。
5、成为VIP后，下载本文档将扣除1次下载权益。下载后，不支持退款、换文档。如有疑问请联系我们。
6、成为VIP后，您将拥有八大权益，权益包括：VIP文档下载权益、阅读免打扰、文档格式转换、高级专利检索、专属身份标志、高级客服、多端互通、版权登记。
7、VIP文档为合作方或网友上传，每下载1次，网站将根据用户上传文档的质量评分、类型等，对文档贡献者给予高额补贴、流量扶持。如果你也想贡献VIP文档。上传文档

Exponentiator Sub-Threshold Design - Harvey Mudd College乘幂运算器的亚阈值设计哈维玛德学院

ExponentiatorSub-Threshold Design Sub-threshold research group: Andrew Danowitz Anu Kohli Autumn Petros-Good James Brown Matthew Weiner Introduction Low power RSA Encryption Modular exponentiation Uses Montgomery multiplication Radix-4 Sub-threshold design Subthreshold Overview Transistors driven at voltages below VT Below VT, current exponentially decreases with decreasing VDD Uses leakage current for operation Subthreshold Motivation Benefits: Ultra-low power Disadvantages: Exponentially slower Sensitive to process variations Performance depends on ambient conditions Applications: Encryption chips on smart-credit cards Pace-makers Watches Wireless sensor nodes System Overview Units: 7 memories Control logic Kernel FIFO Sequencer Design Questions Number of processing elements, p Word Size, w Supply Voltage Choice of Sizes for p and w Goal: Perform 1024-bit RSA encryptions p – # of processing elements (PE) w – word size Logic behind choice: ↑ in p ? higher latencies Minimize area, area is proportional to p*w Want “w” to be a power of 2 Faster encryption ? less leakage from memory n 2pw + w Choice of Sizes for p and w Final Decision: Supply Voltage Test Setup: 5 cascading fanout of 1 gates Tested NAND2, NOR2, NOR3 Only 1 gate input switched Supply Voltage Spice Simulation Swept supply voltage Monte Carlo simulations Results: Requires VDD of 0.280V NOR3 is limiting gate System Overview Units: 7 memories Control logic Kernel FIFO Sequencer Floorplanning – Preliminary Floorplan Objectives: Conservative estimates for cell areas Major busses between cells Optimizing for shorter wire lengths Maintaining size constraints Floorplanning – Preliminary Floorplan Floorplanning – Detailed Floorplans Objectives: Better size estimates for cells Bus widths and locations for all signals Slice plans indicate wire crossings for a single bit-slice Floorplanning – Detailed Floorplans Kernel and FIFO Schematics completed and validated Memories Objectives: Each memory needs