一种用于14 bit SAR ADCDAC设计.docVIP

一种用于14 bit SAR ADCDAC设计 　　摘要:本文设计了用于14bit逐次逼近型模数转换器(SAR ADC)的DAC电路。针对该DAC,介绍一种全差分分段电容阵列结构以缩小DAC的版图面积;高二位权电容采用热码控制,用以改善高位电容在转换时跳变的尖峰以及DAC的单调性;对电容阵列采用数字校准技术,减小电容阵列存在的失配,以提高SAR ADC精度。校准前,SAR ADC的INL达到10LSB,DNL达到4LSB;与校准前相比,校准后,INL 　　关键词:逐次逼近型模数转换器 ;DAC;分段电容阵列;热码控制;数字校准技术 　　 　　A Design of Digital-to-Analog Converter Based on 　　14-bit Successive Approximation Analog-to-Digital Converter 　　 　　LIU Yong-hong1, HE Ming-hua2 　　(1.Fujian Intergrated Circuit Design Centre,Fuzhou 350002 Fujian Province, 　　2.Institute of Physics and Information Engineering,Fuzhou university,Fuzhou 350002, Fujian Province ) 　　 　　Abstract:This paper describes a design of DAC based on 14-bit successive approximation ananlog-to-digital converter(SAR ADC),which uses fully differential segmented capacitor array structure to reduce layout area. Thermal code control is used on sophomore-bit capacitorto improve the high bit capacitor’s jump peak at the time of conversion and the monotoni-city ofDAC. Also,digital calibration technique is used based on the segmented capacitor arraystructure to reduce the mismatch between capacitors and improve the precision of SAR A-DC. Before calibrating,INL and DNL of SAR ADC reach to 10LSB and 4LSB respectively,as compared with pre-calibration, INL is not more than 0.5 LSB ,and DNL not more th-an 0.6 LSB after calibrating.Results of simulation confirms that,DAC design in this paper greately improves p-erformance of SAR ADC. 　　Key words:Successive approximation Analog-to-Digital converter;DAC;Sub-capacitor Array; Thermal code control;Digital Calibration Technique; 　　 　　1引言 　　 　　随着集成电路和通信产业的迅速发展,A/D转换器得到了更加广泛的应用,A/D转换器设计逐渐高速、高精度及低功耗方向发展。而逐次逼近转换器(SAR ADC)具有中等速度(5 MS/s 以下)、中等精度(8～18位)、低功耗和低成本的综合优势, 尤其因制造工艺与现代数字CMOS工艺的兼容性好,易于在较低的工艺成本下实现 ,可广泛应用于现代超大规模集成电路与片上系统 ( system on chip,SOC) ,因而受到人们的高度关注[1]。 ??　[3]中提到,SAR ADC非常适合于低功耗方面的运用,但其缺点是精度低,12 bit以上精度的传统SAR ADC,将占据整个SOC系统大量面积。[8]提到,采用多级分段电容阵列可以减小DAC面积,用线性校准技术可以减小KT/C噪声。 　　本文设计了用于逐次逼近型模数转换器(SAR ADC)的DAC电路。介绍一种全差分