EDA 实验(VHDL语言).docxVIP

一、51位计数器（原理图输入）原理图：仿真图：二、组合逻辑电路：（1）优先8线----3线编码器：源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY encoder8_3 ISPORT(q0,q1,q2,q3,q4,q5,q6,q7:IN STD_LOGIC; Y1,Y2,Y3:OUT STD_LOGIC);END encoder8_3;ARCHITECTURE encoder OF encoder8_3 ISBEGIN y3=q4 OR q5 OR q6 OR q7;y2=q2 OR q3 OR q6 OR q7;Y1=q1 OR q3 OR q5 OR q7;END encoder;仿真图：（2）3线----8线译码器：源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY decoder3_8 IS PORT(G0,G1,G2: IN STD_LOGIC; A: IN STD_LOGIC_VECTOR(2 DOWNTO 0); Y: OUT STD_LOGIC_VECTOR(7 DOWNTO 0));END decoder3_8 ;ARCHITECTURE decoder OF decoder3_8 ISBEGIN PROCESS (G0,G1,G2) BEGIN IF(G0=1 AND G1=0 AND G2=0)THEN CASE A IS WHEN 000 = Y WHEN 001 = Y WHEN 010 = Y WHEN 011 = Y WHEN 100 = Y WHEN 101 = Y WHEN 110 = Y WHEN OTHERS = Y END CASE; ELSE Y END IF;END PROCESS;END decoder;仿真图：（3）8位数据选择器：源程序：LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY data_selector ISPORT(G: IN STD_LOGIC; A: IN STD_LOGIC_VECTOR(2 DOWNTO 0); D0,D1,D2,D3,D4,D5,D6,D7: IN STD_LOGIC; Z1,Z2: OUT STD_LOGIC);END data_selector;ARCHITECTURE selector OF data_selector ISBEGINprocess(A,D0,D1,D2,D3,D4,D5,D6,D7)BEGINIF (G=1) THENZ1=0;Z2=1;ELSIF (G=0 AND A=000)THEN Z1=D0; Z2=NOT D0;ELSIF (G=0 AND A=001)THEN Z1=D1; Z2=NOT D1;ELSIF (G=0 AND A=010)THEN Z1=D2; Z2=NOT D2;ELSIF (G=0 AND A=011)THEN Z1=D3; Z2=NOT D3;ELSIF (G=0 AND A=100)THEN Z1=D4; Z2=NOT D4;ELSIF (G=0 AND A=101)THEN Z1=D5; Z2=NOT D5;ELSIF (G=0 AND A=110)THEN Z1=D6; Z2=NOT D6;ELSIF (G=0 AND A=111)THEN Z1=D7; Z2=NOT D7;END IF;END PROCESS;END selector;仿真图：（4）数值比较器：源程序:LIBRARY IEEE;USE IEEE.STD_LOGIC_1164.ALL;ENTITY data_comparator ISPORT(A:IN STD_LOGIC_VECTOR(3 DOWNTO 0); B:IN STD_LOGIC_VECTOR(3 DOWNTO 0); YA,YB,YC: OUT STD_LOGIC);END data_comparator;ARCHITECTURE compare OF data_comparator IS BEGIN PROCESS (A,B) BEGIN