Layout Tutorial(Layout 教程).pdfVIP

Layout Tutorial The tool we will be using for layout is the Virtuoso Layout editor from Cadence. Layout Overview: Layout is a graphical, dimension-specific representation of an integrated circuit design. The circuit components are drawn using different layers and interconnected with metal traces. The layout provides masking information specifying how the different IC layers are to be fabricated. Fabrication is standardized by a particular process (e.g. TSMC 0.3u). Only certain types of layers are available for a given process. Refer to the following link for a list of TSMC 0.3u layers. /Technical/Layermaps/lm-scmos_scn6m.html The layout is constructed from rectangular layers. The dimensions are measured in units of lambda (not to be confused with the channel length modulation term). Lambda is usually the process length divided by 2. (e.g. lambda = 0.24u/2 = 0.12u) A layout must adhere to a set of rules established by MOSIS. These rules regulate the allowable separation between layers. The rules are specified in units of lambda; therefore, the rules are generalized for any process length. The Virtuoso Layout Editor in Cadence has a design rule checker (DRC). This checker compares your layout with the rules. In any rule is broken, it is referenced by its rule number and displayed in the Cadence Log window. The conflicting area is also high lighted on the layout. These conflicts must be resolved, by changing the separation of the layers in conflict. When a design layout is complete and it passes the DRC, then it can be extracted. Extraction is a process that identifies the components and interconnections from the layout. An Extracted View is created, which contains symbolic representation of the transistors, resistors, capacitor, etc. The Extracted View, like the Schematic Vi