Verilog_HDL(教学PPT).pptVIP

Verilog HDL复杂数字系统设计;例1-1：11111010000序列检测器 module shift(q,s,d,clk); output[11:0] q; output s; input d; input clk; reg[11:0] q; reg s; always @(posedge clk) begin q=q1; q[0]=d; end always @(posedge clk) if(q==12b 11111010000) s=1; else s=0; endmodule ;例1-2列信号发生器。 module generator (out,clk); output[2:0] state; output out; input clk; reg[2:0] state ; reg out; always @(posedge clk) begin state=state+1 ; case(state) 3’b000:out=1; 3’b001:out=1; 3’b010:out=0; 3’b011:out=1; 3’b100:out=0; 3’b101:out=1; 3’b110:out=0; 3’b111:out=0; default: out=0; endcase end endmodule;例1-3：设计一个容量为1kB的RAM。 module memory (d,a,we,rd); inout[7:0] d; input[9:0] addr; input we,rd; wire[7:0] q ; assign d= rd ? q: 8’hzz; lpm_ram_dp0 ram0(d ,a , a ,we,rd,q); endmodule ;第一章 先进先出数据缓冲器设计;;;1.2 状态转换图 采用同步时序 状态机: 3个状态;1.3 FIFO模型设计之一 //FIFO //Size:255Bytes module fifo(clk,nreset,pe,ph,fifo_in,fifo_out,fifo_wr,fifo_rd, busy,empty,full,state,wr,rd); input clk,nreset,fifo_wr,fifo_rd;// input[7:0] fifo_in; output[1:0] state; output empty,full,wr,rd,busy;// output[7:0] fifo_out,pe,ph; reg[1:0] state; reg[7:0] fifo_out; reg wr,rd,empty,full;//fifo write , read ,empty , full reg[7:0]pe,ph; //fifo point:P_end,P_head parameter write=1,read=2,stop=0;;always@(posedge clk) if (nreset==0) begin pe=0;ph=0; end else case(state) stop: if( fifo_wr==1 pe+1!==ph) //write start begin rd=0; wr=1;state=write;busy=1; end else if(fifo_rd==1 pe!==ph) //read start begin wr=0;rd=1;state=read;busy=1; end else begin wr=0;rd=0;state=stop;busy=0; if(ph==pe) empty=1; else if(pe+1==ph) full=1; else begin empty=0; full=0; end end ; write: if( fifo_wr==0 ) //end of write begin pe=pe+1;wr=0;rd=0;stat