A 43-GHZ STATIC FREQUENCY DIVIDER IN 0.13μM STANDARD CMOS.pdfVIP

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A 43-GHZ STATIC FREQUENCY DIVIDER IN 0.13μM STANDARD CMOS.pdf

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A 43-GHZ STATIC FREQUENCY DIVIDER IN 0.13μM STANDARD CMOS

A 43-GHZ STATIC FREQUENCY DIVIDER IN 0.13μM STANDARD CMOS Bangli Liang, Dianyong Chen, Bo Wang, Dezhong Cheng, Tad Kwasniewski Department of Electronics, Carleton University, 1125 Colonel By Dr., Ottawa, ON, K1S 5B6, Canada ABSTRACT The proposed 2:1 frequency divider shown in Fig.1 consists of a master-slave flip-flop (MS-FF) with feedback from its In this paper, a low supply static 2:1 frequency divider output to its input and a 3-stage output buffer (BUFF), based on 0.13μm CMOS is presented. It is designed for 40- which provides better signal waveform, appropriate Gb/s optical communication systems. Current-mode logic amplitude, proper DC level and good output matching. (CML) is adopted because of the higher speed compared to static CMOS and the robustness against common-mode disturbances. This frequency divider is designed with output buffer to drive the external 50Ω loads. On-chip shunt DP peaking (SP) inductors and split-resistor (SR) loads are used DN QP to boost the bandwidth. The frequency divider uses a single QN BUFF Output CKP 1.2-V supply voltage and consumes a total current of 32mA. Input CKN And the chip area is only 0.63mm2 with bonding pads.