现在微处理机-指令级并行-记分牌算法.pptVIP

1.Issue - if no structural haards AND non wAW (no Funtional Unit is going to write this destination register; 1 per clock cycle 2. Read -(RAW) if no instructions is going to write a source register of this instruction (alternatively, no write signal this clock cycle) + gein exection of the instruction; many read ports, so can read many times 3. Execution Complete; multiple during clock cyle 4. Write result - (WAR) If no instructiion is watiing to read the destination register; assume multiple wriite ports; wait for clock cycle to write and tehn read the results; assume can oerlap issue write show clock cyclesneed 20 or so Latency: minimum is 4 through 4 stages study the past if you would define the future. by Confucius LD F0 to output to next LD F0 ADD F0 input to LD F0 3 clocks doing work, 3 overhead (stall, branch, sub) 2009-11-16 What you might have thought 1. 4 stages of instruction execution 2.Status of FU: Normal things to keep track of (RAW structure for busyl): Fi from instruction format of the mahine (Fi is dest) Add unit can Add or Sub Rj, Rk - status of registers (Yes means ready) Qj,Qk - If a no in Rj, Rk, means waiting for a FU to write result; Qj, Qk means wihch FU waiting for it 3.Status of register result (WAW WAR)s: which FU is going to write into registers Scoreboard on 6600 = size of FU 6.7, 6.8, 6.9, 6.12, 6.13, 6.16, 6.17 FU latencies: Add 2, Mult 10, Div 40 clocks Scoreboard Example: Cycle 1 Issue 2nd LD? Scoreboard Example: Cycle 2 Issue MULT? Scoreboard Example: Cycle 3 Scoreboard Example: Cycle 4 Scoreboard Example: Cycle 5 Scoreboard Example: Cycle 6 Read multiply operands? Scoreboard Example: Cycle 7 Scoreboard Example: Cycle 8a (First half of clock cycle) Scoreboard Example: Cycle 8b (Second half of clock cycle) Read operands for MULT SUB? Issue ADDD? Note Remaining Scoreboard Example: Cycle 9 Scoreboard Example: Cycle 10 Scoreboard Example: Cycle 11 Read operands for DIVD? Scoreboard Example: Cycle 12 Scoreboard Example: Cycle