微机原理课件ch10英文.pptVIP

To determine the address range that a device is mapped into: This 2KB memory segment maps into the reset location of the 8086/8088 (FFFF0H). NAND gate decoders are not often used Large fan-in NAND gates are not efficient Multiple NAND gate ICs might be required to perform such decoding Rather the 3-to-8 Line Decoder (74LS138) is more common. * 第*页 Note that all three Enables (G2A, G2B, and G1) must be active, e.g. low, low and high, respectively. Each output of the decoder can be attached to an 2764 EPROM (8K×8). * 第*页 * 第*页 The memory systems sees the 8088 as a device with: 20 address connections (A19 to A0). 8 data bus connections (AD7 to AD0). 3 control signals, IO/M, RD, and WR. Well look at interfacing the 8088 with: 32K of EPROM (at addresses F8000H through FFFFFH). 512K of SRAM (at addresses 00000H through 7FFFFH). The EPROM interface uses a 74LS138 (3-to-8 line decoder) plus 8 2732 (4K×8) EPROMs. * 第*页 * 第*页 * 第*页 * 第*页 * 第*页 * 第*页 * 第*页 * 第*页 8088 * 第*页 8086 * 第*页 8086 * 第*页 8086 * 第*页 8086 * 第*页 * 第*页 * 第*页 * 第*页 * 第*页 Given the address range, how many chip is needed to contruct the memory space? Given the specific address, how to arrange the memory chip? Given the connected memory chip diagram, how to calculate the address range? * 第*页 2,3,7,19,22,27,31 * 第*页 * The Intel Microprocessors Instructor：Dr. Alex Yu Memory Devices Address Decoding 8086 Memory Interface Keynotes: Address Decoding * 第*页 Type ROM: Read-only memory RAM: Read-Write memory Four commonly used memories ROM Flash, EEPROM Static RAM (SRAM) Dynamic RAM (DRAM), SDRAM, RAMBUS, DDR RAM Generic pin configuration * 第*页 Address Pins The number of address pins is related to the number of memory locations 1M for 20 pins Data Pins The data pins are typically bi-directional in read-write memories. The number of data pins is related to the size of the memory location. For example, an 8-bit wide (byte-wide) memory device has 8 data pins. Catalog listing of 1K X 8 indicate a byte addressable 8