verelog闹钟设计.pptVIP

闹钟设计 小组成员： 赵亚 卢成 简虎 潘楠楠 王泽 赵峰 作品简介 功能一：时钟计时 功能二：调整时间 功能三：闹钟 程序代码 顶层模块：naozhong 按键编码器：anjianbianma 计时器：jishiqi 闹钟：clock 分频器：fenpinqi 显示器：LED 控制器：kongzhiqi 顶层模块 module naozhong(clk,set,TIME,alarm,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,led1,led2,led3,led4,fengming,led_in1,led_in2,led_in3,led_in4); input clk,set,TIME,alarm,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9; output[6:0] led1,led2,led3,led4,fengming; output[3:0] led_in1,led_in2,led_in3,led_in4; wire clkout; wire[6:0] led1,led2,led3,led4; wire[3:0] time_h_s,time_h_g,time_m_s,time_m_g,clock_h_s,clock_h_g,clock_m_s,clock_m_g,hour_s,hour_g,minute_s,minute_g,led_in1,led_in2,led_in3,led_in4; wire fengming; fenpinqi a1(clk,clkout); anjianbianma b1(clk,set,TIME,alarm,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,hour_s,hour_g,minute_s,minute_g); clock c1(clk,set,TIME,alarm,hour_s,hour_g,minute_s,minute_g,clock_h_s,clock_h_g,clock_m_s,clock_m_g); jishiqi d1(clk,set,TIME,alarm,time_h_s,time_h_g,time_m_s,time_m_g,hour_s,hour_g,minute_s,minute_g); kongzhiqi e1(clk,set,TIME,alarm,time_h_s,time_h_g,time_m_s,time_m_g,clock_h_s,clock_h_g,clock_m_s,clock_m_g,hour_s,hour_g,minute_s,minute_g,led_in1,led_in2,led_in3,led_in4,fengming); LED f1(clkout,led_in1,led_in2,led_in3,led_in4,led1,led2,led3,led4); endmodule 按键编码器 module anjianbianma(clkout,set,TIME,alarm,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9,hour_s,hour_g,minute_s,minute_g); input clkout,set,TIME,alarm,s0,s1,s2,s3,s4,s5,s6,s7,s8,s9; output[3:0] hour_s,hour_g,minute_s,minute_g; reg[3:0] hour_s,hour_g,minute_s,minute_g; reg R; reg[2:0] count; reg[3:0] S; always@(posedge clkout) begin if(set==1) begin hour_s=0; hour_g=0; minute_s=0; minute_g=0; R=1; end if(R==1) begin if(TIME==1||alarm==1) begin count=0; R=0; end else if(s0==1) begin S=0;count=count+1; end else if(s1==1) begin S=1;count=count+1; end else if(s2==1) begin S=2;count=count+1; end else if(s3==1) begin S=3;count=count+1; end else if(s4==1) begin S=4;count=count+1; end else if(s5==1) begin S=5;count=count+1; end