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Synthesizer (PLL) Design Larry B. Li Comlent Technology, Inc. Outline Overview of CL3010 Design Digital Design flow of Fractional Synthesizer PLL Basic Phase Noise in PLL Delta-Sigma Modulator Spurious in PLL Charge Pump Design Summary PHS System with CL3010B +PA CL3010X3 Schematic Block Diagram of Fractional Synth. Fractional-N Synthesizer Block Diagram for Delta Modulator Delta Sigma Schematic Delta-Sigma Layout Simple PLL System Type I PLL Model Type I PLL Settling Time Type I PLL Stability One pole at origin s=0 Another pole is –ωLPF Phase margin should be 65o Open Loop D C gain is infinity Frequency acquisition range is limited (~ ωLPF) Type II PLL CP PLL basic CP PLL basic (2) CP PLL basic (3) Phase noise at input Noise in VCO Noise in PLL Frequency Synthesizer Phase Noise calculations Phase Noise from Clock Buffer Phase Noise from Charge Pump During lock time, change pump is on for short time TP. Charge will be off for most of time. Noise contribution is only during the on time. Phase Noise from VCO Fractional Synthesizer Δ-Σ Modulator Noise contribution for Δ-Σ Modulator Reference Spurious in PLL Reference Spurious Calculation Kvco=85MHz/V, a1=1mV, Fvco=3800MHz, 2nd order Filter 4th order filter for PLL Spurs from Current Leakage Charge Pump Current Mismatch Current mismatch will generate net charge to control line. Net current will be zero when PLL is locked. Up/DN signal will be different. Charge Sharing in Charge Pump Charge injection from switches Parasitic capacitance difference between PMOS and NMOS. Charge Pump Design Charge Pump Design Charge Pump Circuit Charge Pump Design Consideration Mismatch between up down current Charge injection the control line Voltage compliance Less current consumption Minimize the noise current Leakage current when charge pump tri-stated ESD consideration for charge pump output. *Comlent Technology, Inc. After PLL Settle fVCO=N·fREF If frequency Change 20MHz, then settle to 1kHz Charge Pump based PLL call Type II