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3.7综合练习 例1：一位二进制计数加七段译码电路AHDL设计如下，该设计中调用了老功能模块”4count”和七段译码器设计文件7segment.tdf。 设计源文件： FUNCTION 4count(clk,clrn,setn,ldn,cin,dnup,d,c,b,a) %库中有此模块% RETURNS(qd,qc,qb,qa,cout); FUNCTION 7segment(i3,i2,i1,i0) %见前面的例题% RETURNS(g,f,e,d,c,b,a); SUBDESIGN 4cnt7s ( clk,dnup :INPUT; sa,sb,sc,sd,se,sf,sg,out,xs[3..0] :OUTPUT; ) VARIABLE counter : 4count; decoder : 7segment; BEGIN counter.clk =clk; counter.dnup =dnup; decoder.i[3..0]=counter.(qd,qc,qb,qa); xs[]=counter.(qd,qc,qb,qa); (sg,sf,se,sd,sc,sb,sa)=decoder.(g,f,e,d,c,b,a); out=counter.cout; END; 该设计的仿真结果见图3.7.1。 图3.7.1 例2：N位计数译码电路 四位十进制计数器AHDL设计文件(pdec9999.tdf)： SUBDESIGN pdec9999 ( clk, ena, clrs : INPUT; a[15..0] : OUTPUT; ) VARIABLE count1[3..0] : DFF; count2[3..0] : DFF; count3[3..0] : DFF; count4[3..0] : DFF; BEGIN count1[].clk = clk; count1[].clrn = clrs; count2[].clk = clk; count2[].clrn = clrs; count3[].clk = clk; count3[].clrn = clrs; count4[].clk = clk; count4[].clrn = clrs; IF ena THEN if count1[]==B1001 then count1[] =B0000; ELSE count1[].d = count1[].q + 1; END IF; ELSE count1[].d = count1[].q; END IF; IF ena THEN if count1[]==B1001 then if count2[]==B1001 then count2[] =B0000; ELSE count2[].d = count2[].q + 1; END if; ELSE count2[].d = count2[].q; end if; ELSE count2[].d = count2[].q; END IF; IF ena THEN if count2[]==B1001 count1[]==B1001then if count3[]==B1001 then count3[] =B0000; ELSE count3[].d = count3[].q + 1; end if; ELSE count3[].d = count3[].q; end if; ELSE count3[].d = cou