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design of energy aware adder circuits considering random intra-die process variations能源意识到加法器电路设计考虑随机intra-die过程变化
J. Low Power Electron. Appl. 2011, 1, 97-108; doi:10.3390/jlpea1010097 OPEN ACCESS Journal of Low Power Electronics and Applications ISSN 2079-9268 /journal/jlpea/ Article Design of Energy Aware Adder Circuits Considering Random Intra-Die Process Variations Marco Lanuzza, Fabio Frustaci, Stefania Perri and Pasquale Corsonello * Department of Electronics, Computer Science and Systems (DEIS), University of Calabria, Arcavacata di Rende-87036-Rende (CS), Italy; E-Mails: lanuzza@deis.unical.it (M.L.); ffrustaci@deis.unical.it (F.F.); perri@deis.unical.it (S.P.) * Author to whom correspondence should be addressed; E-Mail: p.corsonello@unical.it; Tel.: +39-0984-494708; Fax: +39-0984-494834. Received: 25 November 2010; in revised form: 18 March 2011 / Accepted: 1 April 2011 / Published: 6 April 2011 Abstract: Energy consumption is one of the main barriers to current high-performance designs. Moreover, the increased variability experienced in advanced process technologies implies further timing yield concerns and therefore intensifies this obstacle. Thus, proper techniques to achieve robust designs are a critical requirement for integrated circuit success. In this paper, the influence of intra-die random process variations is analyzed considering the particular case of the design of
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