EDAVHDL顺序语句(program).pptVIP

第6章 VHDL顺序语句 library ieee; use ieee.std_logic_1164.all; entity reset_dff2 is port( clk,reset : in std_logic; d : in std_logic; q : out std_logic); end reset_dff2; architecture rtl of reset_dff2 is begin process begin wait on clk, reset; if (reset = ‘1’ ) then q = ‘0’; elsif（clk’event and clk=‘1’) then q = d; end if; wait on clk, reset; end process; end rtl; process begin wait until clk’event and clk=‘1’； if (reset = ‘1’ ) then q = ‘0’; else q = d; end if; end process; end rtl; library ieee; use ieee.std_logic_1164.all; entity clk_generator is port( clk : out std_logic); end clk_generator; architecture example of clk_generator is begin process begin wait for 125 ns; clk = ‘0’; wait for 125 ns; clk = ‘1’; end process; end rtl; architecture behave of example is signal a,b : std_logic; begin a = ‘0’; label1: process begin wait until b = ‘1’; a = ‘1’ after 10 ns; wait until b = ‘0’; a = ‘0’ after 10 ns; end process; label2: process begin wait until a = ‘0’; b = ‘0’ after 10 ns; wait until a = ‘1’; b = ‘1’ after 10 ns; end process; end behave; library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity adder is port( q1, q2 : in std_logic_vector(7 downto 0); cs : in std_logic; q : out std_logic_vector(7 downto 0)); end adder; architecture behave of adder is begin process(cs) begin if ( cs = ‘1’ ） then q = q1 + q2; end if; end process; end behave; entity mux2 is port( d0, d1 : in std_logic_vector(3 downto 0); sel : in std_logic; q : out std_logic_vector(3 downto 0)); end mux2; architecture rtl of mux2 is begin