测试卡代码表（Test card code table）.docVIP

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测试卡代码表（Test card code table）.doc

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测试卡代码表（Test card code table）

测试卡代码表（Test card code table） 1, PhoenexBIOS Code： 02: check the real model. 04: confirm the CPU type. 06: initialize the system hardware. 08: initializes the chipset register with the initial POST value. 09: set the identifier in POST. 0A: initializes the CPU register. 0C: initialize CACHE to the initial POST value. 0E: initialize I/O. 10: initialization power management. 11: load the interactive register with the initial POST value. 12:UserPatch0 skip. 14: initialize the keyboard controller. 16:BIOS ROM check and. 18:8254 timer initialization. 1A:8237DMA controller initialization. 1C: reset programmable interrupt controller. 20: Test DRAM refresh. 22: Test 8742 keyboard controller. 24: set the ES fragment to register to 4GB. 28: test, DRAM. 2A: clear 512K basic memory. 2C: clear the address register of the 512K base memory. 2E: Test 512K basic memory. 32: test the CPU bus clock frequency. 34:CMOS RAM failed to read and write (this usually indicates a problem, such as not being addressed accurately on the ISA bus) 37: re initialize chipset. 38: call system BIOS ROM. 39: re initialization CACHE. 3A: check CACHE. 3C: configure advanced chipset registers. 3D: load the interactive register with the CMOS value. 40: sets the initial CPU speed. 42: initialize the interrupt vector. 44: initial BIOS interrupt. 46: check ROM copyright. 47: initializes the management for the PCI option ROMs. 48: check video configuration by CMOS. 49: initializes the PCI bus and device. 4A: initialize video cards in all systems. 4C: call video BIOS ROM. 4E: displays copyright information. 50: displays the CPU type and speed. 52: Test keyboard. 54: set the click key to enable. 56: enable keyboard. 58: check standby interrupt. 5A: display prompt, press F2 to set. 5C: test the 640K between 512 and RAM. 60: Test extended memory. 62: Test extended memory address line. 64:UserPatch1 skip. 66: configure advanced buffer registers. 68: enable external and CPU CACHES. 69: initializes the SMI handler. 6A: