Xilinx IP核设计FIR滤波器.docxVIP

Xilinx IP核设计FIR滤波器ISE版本12.4启动ISEFile-New ProjectNextNext-Finish在ISE的设计启动视图中在空白处右键，选择New Source，弹出对话框Next，弹出对话框Next-FinishNextNextNext（滤波器的详细信息）Generate（生成FIR滤波器IP核）在ISE的设计启动视图可以看到生成的IP核在ISE设计启动视图中右键，New SourceNext-Next-Finish在文件中编辑Verilog`timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////// Company: // Engineer: // // Create Date: 14:40:35 04/18/2011 // Design Name: // Module Name: fir // Project Name: // Target Devices: // Tool versions: // Description: //// Dependencies: //// Revision: // Revision 0.01 - File Created// Additional Comments: ////////////////////////////////////////////////////////////////////////////////////module fir(s_axis_data_tready, s_axis_data_tvalid, m_axis_data_tvalid, aclk, m_axis_data_tdata, s_axis_data_tdata);outputs_axis_data_tready;inputs_axis_data_tvalid;outputm_axis_data_tvalid;inputaclk;output [23 : 0] m_axis_data_tdata;input [15 : 0] s_axis_data_tdata; fir16 fir16(.s_axis_data_tready(s_axis_data_tready),.s_axis_data_tvalid(s_axis_data_tvalid),.m_axis_data_tvalid(m_axis_data_tvalid),.aclk(aclk),.m_axis_data_tdata(m_axis_data_tdata),.s_axis_data_tdata(s_axis_data_tdata));endmodule在ISE设计启动视图右键，New SourceNext-Next-Finish编辑测试文件fir_tb`timescale 1ns / 1ps////////////////////////////////////////////////////////////////////////////////// Company: // Engineer://// Create Date: 15:03:58 04/18/2011// Design Name: fir// Module Name: F:/Xilinx/12.4/ISE_DS/project/Firfilter/fir_tb.v// Project Name: Firfilter// Target Device: // Tool versions: // Description: //// Verilog Test Fixture created by ISE for module: fir//// Dependencies:// // Revision:// Revision 0.01 - File Created// Additional Comments:// ////////////////////////////////////////////////////////////////////////////////modulefir_tb;// Inputsregs_axis_data_tvalid;regaclk;reg [15:0] s_axis_data_tdata;reg [15:0] Mem[37:0];// Outputswires_axis_data_tready;wirem_axis_data_tvalid;wire [23:0] m_axis_data_tdata;integerk,i;// Ins