VHDL仿真课件.pptVIP

VHDL仿真;本章内容;13.1使用ModelSim进行VHDL仿真;library IEEE; use IEEE.STD_LOGIC_1164.all; use ieee.std_logic_unsigned.all; entity cnt16 is port(rst : in STD_LOGIC; clk : in STD_LOGIC; q : out STD_LOGIC_VECTOR(3 downto 0) ); end cnt16; architecture cnt16 of cnt16 is signal q_tmp: STD_LOGIC_VECTOR(3 downto 0); begin process(clk,rst) begin if rst=1 then q_tmp=(others=0); elsif clkevent and clk=1 then q_tmp=q_tmp+1; end if ; end process; q=q_tmp; end cnt16;;1.启动ModelSim;2. 建立仿真工程项目;3. 编译仿真文件;4. 装载仿真模块和仿真库;5. 执行仿真;采用手动方式编辑输入波形 ;采用测试向量（testbench）进行仿真;library ieee; use ieee.std_logic_1164.all; ENTITY cnt16_source IS PORT (clk,rst : OUT STD_LOGIC); end cnt16_source; ARCHITECTURE cnt16_source OF cnt16_source is constant cycle:Time := 10 ns; BEGIN process begin clk = 0; wait for cycle/2; clk = 1; wait for cycle/2; end process; process begin rst = 1; wait for cycle*5; rst = 0; wait; end process; END cnt16_source;;时钟与复位信号生成;仿真文件 ;使用ModelSim进行VHDL仿真 ;软件演示;13.2 Textio程序包;书写格式;读文件;从文件变量中读一行数据;从行变量中读取一个数据;实例;architecture test_textio of test_textio is constant clk_cycle: time:=10ns; file f1: text is in clk_source.dat; begin process variable li : line; Variable j,k : integer; variable clk_tmp:std_logic; begin k:=0; loop_clk:while k100 loop readline(f1,li); read(li,clk_tmp); clk=clk_tmp; wait for clk_cycle; k:=k+1; end loop; end process; process begin rst=1; wait for 2*clk_cycle; rst=0; wait; end process; end test_textio;;写一行到输出文件;写一个数据至行;13.3使用ModelSim对QuartusII设计项目进行仿真