arm 的指令结构（The instruction structure of arm）.docVIP

arm 的指令结构（The instruction structure of arm） The instruction structure of ARM The ARM microprocessor supports two instruction sets in the newer architecture: the ARM instruction set and the Thumb instruction set. The ARM instruction is 32 bits long, and the Thumb instruction is 16 bits long. The Thumb instruction set is a subset of the ARM instruction set, but saves 30% to over 40% of storage space compared to the equivalent ARM code and has all the advantages of 32 bit code. ARM program status register Source: National Business Network Author: unknown The ARM architecture contains a current program status register (CPSR) and five backup program status registers (SPSRs). The backup program status register is used for exception handling, including: Save the current operation information in ALU - controlling, allowing, and disabling interrupts - set the processors run mode Flags (Condition Code) N, Z, C and V are condition code mark bits. Their contents can be changed by the results of arithmetic or logical operations, and can determine whether an instruction is executed. In the ARM state, most instructions are conditional. In the Thumb state, only branch instructions are conditionally executed. Control bit The low 8 bits of PSR (including I, F, T, and M[4:0]) are called control bits, and these bits can be changed when an exception occurs. If the processor runs privileged mode, these bits can also be modified by the program. Interrupt disable bits I, F: I=1 prohibits IRQ interrupts; F=1 prohibits FIQ interrupts. - T flag bit: this bit reflects the processors running state. For the ARM architecture, V5 and more versions of the T family of processors, when the bit is 1, the program runs in the Thumb state, or else it runs in the ARM state. For a non T series processor of V5 and over ARM versions, when the bit is 1, the next instruction is executed to cause a defined instruction exception; when the bit is 0, the operation is running in the ARM state. Run mode bits M[4:0]: