fpga ddr2读写控制器时序代码（FPGA DDR2 read and write controller timing code）.docVIP

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fpga ddr2读写控制器时序代码（FPGA DDR2 read and write controller timing code）.doc

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fpga ddr2读写控制器时序代码（FPGA DDR2 read and write controller timing code）

fpga ddr2读写控制器时序代码（FPGA DDR2 read and write controller timing code） The following is my example of a single data written in DDR, with the state machine to achieve, has been verified! /*****************************************************************************/ The 16bytes / / Ram register write data DDR Always @ (posedge c3_clk0) Begin If (c3_rst0 c3_calib_done ||!) Begin C3_p0_wr_en=1b0; C3_p0_wr_mask=16d0; C3_p0_wr_data=128d0; Ddr_write_busy =1b0; C3_p0_cmd_en_w=1b0; C3_p0_cmd_instr_w=3d0; C3_p0_cmd_bl_w=6d0; C3_p0_cmd_byte_addr_w=30d0; Ddr_write_state=write_idle; End Else Begin Case (ddr_write_state) Write_idle: Begin C3_p0_wr_en=1b0; C3_p0_wr_mask=16d0; If (ddr_wr_req) / / if you write a DDR request Begin Ddr_write_busy=1b1; //ddr write data busy flag Ddr_write_state=write_fifo; C3_p0_wr_data=ddr_wdata_reg; / / to write DDR data End End Write_fifo: Begin If (c3_p0_wr_full!) such as P0 / / write the FIFO data with Begin C3_p0_wr_en=1b1; Ddr_write_state=write_data_done; End End Write_data_done: Begin C3_p0_wr_en=1b0; Ddr_write_state=write_cmd_start; End Write_cmd_start: Begin C3_p0_cmd_en_w=1b0; C3_p0_cmd_instr_w=3b010; //010 is write command C3_p0_cmd_bl_w=6d0; //burst length is 1 128bit data C3_p0_cmd_byte_addr_w=c3_p0_cmd_byte_addr_w+16; Address / / 16 Ddr_write_state=write_cmd; End Write_cmd: Begin If (c3_p0_cmd_full!) / / if dissatisfied with the command FIFO Begin C3_p0_cmd_en_w=1b1; / / write enable command Ddr_write_state=write_done; End End Write_done: Begin C3_p0_cmd_en_w=1b0; Ddr_write_state=write_idle; Ddr_write_busy=1b0; End Default: Begin C3_p0_wr_en=1b0; C3_p0_cmd_en_w=1b0; C3_p0_cmd_instr_w=3d0; C3_p0_cmd_bl_w=6d0; Ddr_write_state=write_idle; End Endcase; End End Sigadsp published in 2013-4-23 20:26:25 | only see the author Here is an example of reading a single DDR data that has been validated /*****************************************************************************/ //DDR data read processor Always @ (posedge c3_clk0) Begin If (c3_rst0 c3_