CortexM4内核及DSP指令.pdfVIP

STM32F4 Core, DSP, FPU Library An introduction of the Cortex-M4 An introduction of some DSP instructions Content  An introduction to the Cortex-M4 Core  And introduction to some of the DSP instructions 2 Content  An introduction to the Cortex-M4 Core  And introduction to some of the DSP instructions 3 Cortex-M4 processor microarchitecture  ARMv7ME Architecture  Thumb-2 Technology  DSP and SIMD extensions  Single cycle MAC (Up to 32 x 32 + 64 - 64)  Optional single precision FPU  Integrated configurable NVIC  Compatible with Cortex-M3  Microarchitecture  3-stage pipeline with branch speculation  3x AHB-Lite Bus Interfaces  Configurable for ultra low power  Deep Sleep Mode, Wakeup Interrupt Controller  Power down features for Floating Point Unit  Flexible configurations for wider applicability  Configurable Interrupt Controller (1-240 Interrupts and Priorities)  Optional Memory Protection Unit  Optional Debug Trace 4 Different Core Cortex-M3 Cortex-M4 Architecture Version v7M v7ME Instruction set Thumb + Thumb-2 Thumb + Thumb-2, architecture DSP, SIMD, FP DMIPS/MHz 1.25 1.25 Integrated NVIC Yes Yes Number interrupts 1-240 + NMI 1-240 + NMI Interrupt priorities 8-256 8-256 Single Cycle Multiply Yes Yes Hardware D